Add a hook to act when the a device is going in tablet mode and back.
BUG=chromium:606718
BRANCH=kevin
TEST=Test with evtest that an event is sent to the AP.
Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380412
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We don't really have the ability to build the latest signer yet, but
this should not stop us from being able to build a properly signed
image using the ec makefiles.
As a stopgap measure the suggestion is to keep the latest signer
binary in ~/bin/codesigner in chroot, then with this patch applied
invoking make with CR50_DEV=1 will cause the proper sighner used and
proper signing procedure followed.
The signed targets need to be built in series to avoid concurrent use
of the signer fob, an addition dependency is being added to enforce
that.
BRANCH=none
BUG=chrome-os-partner:55557
TEST=ran make as follows:
CR50_DEV=1 make BOARD=cr50
touched the fob when requested, uploaded the generated
build/cr50/ec.bin on a kevin-tpm2 using usb_updater, and observed
it boot properly with the new version.
Change-Id: Ia9494bdc60b4bd3b8e5e09cbcbd8b27409c739d2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376885
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enabled the trickle charging mode by setting the VPRECHG_TH_SET
register[0x18H] to board specific battery voltage minimum value.
When the battery voltage drops below the battery voltage minimum
value, trickle charging is enabled.
BUG=chrome-os-partner:56684
BRANCH=none
TEST=Manually verified on Reef. Drained the battery below battery
voltage minimum value. On plugging in the charger, State
Machine Status register CHGSTM_STATUS [0x00h] is 0x01 which
indicates, current state of the charger state-machine is in
Trickle-Charge condition.
Change-Id: Ic4b985c71ff68ea4f5ab22e18feab03d776ec134
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/376939
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To be able to parse binary panicinfo from feedback reports, we need
a host tool:
- Move panicinfo generic parsing functions to a separate C file
- Create a new host utility to parse panicinfo
BRANCH=none
BUG=chromium:643062
TEST=base64 -d | ec_parse_panicinfo
Change-Id: Idd8560a2894f270d0ab3a9f654c333135759e57f
Reviewed-on: https://chromium-review.googlesource.com/379639
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reads of the TPM fifo by the Host are done in chunks of up to 63 bytes
at a time. The existing routine used to copy data read from the TPM
layer to the I2CS fifo operates one byte at a time. This method is
fine for single and four byte register reads. However, for larger
buffers the performace can be improved by aligning the the fifo write
pointer to be at a word boundary.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Utilized test code on the host to initiate TPM fifo reads of various
lengths and added timing markers on the Cr50 to compare performance
between the existing byte at a time and the new full buffer write
funciton. Verifed that the fifo reads will still correct and compared
the time consumed copy TPM fifo data to the I2CS HW fifo.
This test processed 1910 bytes over 34 fifo reads.
Byte at a time method:
1910 bytes: 6375 uS: Avg Time = 3.233 uS per byte
Full buffer write:
1910 bytes: 3009 uS: Avg Time = 1.57 uS per byte
Change-Id: I3a47a350ab7af740a452fd115c33117b453b9611
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377663
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This CL adds support for reading of TPM fifo registers. Since I2C does
not provide means to communicate how many bytes the host wants to read
there must be some handshake involved between the host and Cr50.
The method added by this CL to allow Host reads of the TPM fifo
assumes the following steps:
1. Host reads burstcount from Cr50 (which will be set to default 63)
2. Host reads 1st 10 bytes of the TPM response.
3. Cr50 will copy MIN(burstcount, msg_len) bytes into its I2CS HW fifo
4. Host computes msg_len and calculates amount of data still buffered
5. Host does a TPM fifo read of buffered data only
(The following steps are repeated until the response read is complete)
6. Host reads burstcount from STS register.
7. Host issues read of burscount bytes from TPM fifo
8. I2CS will copy burstcount amount of bytes in to I2CS HW fifo
9. TPM layer sets burstcount to MIN(63, remaining msg bytes)
The version register is treated similar to a fifo access. The data
written or the number of bytes is a don't care, but there must be
at least one byte of data written with the version register write.
In the case of reads, the host must read burstcount bytes of the
version register. If burstcount is longer than the Cr50 version string
there is no issue because the version register read function always
returns the number of bytes requested, stuffing in 0s once the end of
the version string is reached.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Created test code in coreboot that exercises TPM register reads and
writes. In addition, created a means to spoof a TPM cmd send and
response read by Host. For these tests the header length is defined as
10 bytes and used 3 different payload lengths. The results for a
payload length of 256 and 39 (message < 63) are shown below. Note the
0xaa and 0x55 have been inserted by the TPM spoof code on the host to
mark the end of the header.
=================================================
Cr50 TPM Register Read tests
TPM Access = 0x0
TPM2 STS = 0x4003f80
TPM2 DID_VID = 0x281ae0
DID = 0x28, VID = 0x1ae0
Ver segment read 1, ret = 0
Version: B2:0 RO_A:0.0.1/84e2dde7 RW_A:0.0.1/cr50_v1.1.5151-acaef21+
=================================================
TPM Cmd: 266 bytes, Hdr = 10, Payload = 256 (last = ff)
TPM STS: Sending command_ready
fifo wr: burstcount = 63
fifo wr: Sent TPM Cmd: len = 266 bytes
TPM STS: Sending TPM GO
TPM STS: data_avail set
TPM STS: 04 00 3f d0: burst = 63
fifo rd: Msg_len = 266
fifo rd: Hdr Len = 10, fifo_adjust = 53
fifo rd: Drained Cr50 HW fifo of 53 bytes
fifo rd: burst = 63
fifo rd: burst = 63
fifo rd: burst = 63
fifo rd: burst = 14
fifo rd: complete 266 byte msg read
[0000]: 00 00 00 00 01 0a 00 00 aa 55 00 01 02 03 04 05
[0010]: 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15
[0020]: 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25
[0030]: 26 27 28 29 2a 2b 2c 2d 2e 2f 30 31 32 33 34 35
[0040]: 36 37 38 39 3a 3b 3c 3d 3e 3f 40 41 42 43 44 45
[0050]: 46 47 48 49 4a 4b 4c 4d 4e 4f 50 51 52 53 54 55
[0060]: 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65
[0070]: 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75
[0080]: 76 77 78 79 7a 7b 7c 7d 7e 7f 80 81 82 83 84 85
[0090]: 86 87 88 89 8a 8b 8c 8d 8e 8f 90 91 92 93 94 95
[00a0]: 96 97 98 99 9a 9b 9c 9d 9e 9f a0 a1 a2 a3 a4 a5
[00b0]: a6 a7 a8 a9 aa ab ac ad ae af b0 b1 b2 b3 b4 b5
[00c0]: b6 b7 b8 b9 ba bb bc bd be bf c0 c1 c2 c3 c4 c5
[00d0]: c6 c7 c8 c9 ca cb cc cd ce cf d0 d1 d2 d3 d4 d5
[00e0]: d6 d7 d8 d9 da db dc dd de df e0 e1 e2 e3 e4 e5
[00f0]: e6 e7 e8 e9 ea eb ec ed ee ef f0 f1 f2 f3 f4 f5
[0100]: f6 f7 f8 f9 fa fb fc fd fe ff 00 00 00 00 00 00
=================================================
TPM Cmd: 49 bytes, Hdr = 10, Payload = 39 (last = 26)
TPM STS: Sending command_ready
fifo wr: burstcount = 63
fifo wr: Sent TPM Cmd: len = 49 bytes
TPM STS: Sending TPM GO
TPM STS: data_avail set
TPM STS: 04 00 3f d0: burst = 63
fifo rd: Msg_len = 49
fifo rd: Hdr Len = 10, fifo_adjust = 39
fifo rd: Drained Cr50 HW fifo of 39 bytes
fifo rd: complete 49 byte msg read
[0000]: 02 00 00 00 00 31 00 00 aa 55 00 01 02 03 04 05
[0010]: 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15
[0020]: 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 22 23 24 25
[0030]: 26 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Change-Id: I0e05156d6012c6dc86844e4c0ea80cc04f45734a
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374528
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Removed 3 TPM register definitions which were not used in
tpm_registers.c and added missing entries to the I2CS translation
table for TPM register address lookup.
Moved the SPI specific locality 0 offset from tpm_registers.c to
sps_tpm.c so the register defines in tmp_registers.c can be
common to both the SPS and I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
For I2CS verification on Reef AP console used the command 'i2cget
-y 8 0x50 <addr> b' to read both the TPM access and RID register.
For SPI verifcation updated Cr50 FW on Kevin and verified that the
AP successfully boots. Additionally, issued the command from the
Kevin console 'trunks_client --own' and got the following console
output without any errors being listed.
[INFO:tpm_utility_impl.cc(1692)] CreateStorageRootKeys: Created RSA SRK.
[INFO:tpm_utility_impl.cc(1735)] CreateStorageRootKeys: Created ECC SRK.
Change-Id: Ib0b70e22cd46de2c59bd2e73f3c9aebd661e66c4
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/368621
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This CL includes changes in Cr50 required to support TPM via
the I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Limited testing so far. Verified that the I2CS interface is
initialized properly and that register reads occur when
initiated on the AP console via command i2cget -y 8 0x50 0x1 w
Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e
Reviewed-on: https://chromium-review.googlesource.com/356241
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Remove timeout to avoid fetching unknown instruction from e-flash
and causing exception.
Also fixed:
- To make sure immu(dynamic cache) is reset after a erasing/writing
operation.
- Verify function is in critical section.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: "flasherase" and "flashwrite".
Change-Id: I0c84282ac4689cd762159071afae3efeea31d281
Reviewed-on: https://chromium-review.googlesource.com/380500
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If we're sourcing 5V to the port, consider the port as not providing
power, for the purpose of VBUS / BC1.2 detection.
BUG=chrome-os-partner:55432
BRANCH=None
TEST=Manual on kevin, attach legacy peripheral in one port, zinger in
the other, run "reboot" on EC console, and verify zinger port is
selected as charge port. Also attach Apple charge-thru accessory w/o
charger plugged, verify that charge manager is not informed of a BC1.2 /
VBUS supplier.
Change-Id: Ifbe587215f28756760e7106e1a00dd96319438e3
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380324
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Port USB firmware update to stm32f4 dwc usb from st usb.
This includes usb dwc usb stream inplementation, generic
endpoint interfaces, and the sweetberry test case.
BUG=chromium:608039
TEST=usb update works
BRANCH=None
Change-Id: Ia26e4f7e990ee64991468799c99b036f5f32190f
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/377520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To save space of working image, make the console memory commands
optional.
BRANCH=veyron
BUG=b:27849483
TEST=Compile, save 320 bytes.
Change-Id: Ia538b30b4c06955c44b29eb22ed1a09fad83bd9e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379115
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The long life scratch register storing the board properties is not
cleared after a hard reset. This change clears the properties before
updating them, so we can reset the properties entirely instead of just
adding to them.
BUG=none
BRANCH=none
TEST=Update Cr50 with an image. Remove one of the board properties it
uses and verify that property has been removed once you update it.
Change-Id: I078dc1443d9f2e7f8761159906e1a277d79cb3cb
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380433
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
CONFIG_FLASH_NVMEM_SIZE was set to CFG_TOP_SIZE and then the partition
size was computed by dividing this value by 2. Changed this so that
now the partition size is set to CFG_TOP_SIZE and the total size is
the partition size * 2. Also reduced the CFG_TOP_SIZE to 0x4000 as
that should be plenty for TPM requirements and leaves room for future
gnubby use.
BRANCH=none
CQ-DEPEND=CL:379076
BUG=chrome-os-partner:56798
TEST=manual
Tested on Kevin, erased the existing NvMem area and verified that TPM
was still manufactured and executed the command: trunks_client --own
Erased parition 0 and 1 in the new locations and repeated the tests.
Change-Id: Ie8910bec641d8d1ff390be5b03b430bf39d18404
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379095
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
TPM2.0 needs more NvMem space and currently the whole block is
contiguous in memory with 2 partitions. This CL removes the
requirement that the partitions are in contiguous which allows for 1
partition to placed at top of RW_A and the other at RW_B.
This CL does not change the size of each partition as that will be
done in a subsequent CL.
BRANCH=none
BUG=chrome-os-partner:56798
TEST=manual
Tested with the unit test 'make runtests TEST_LIST_HOST=nvmem' and
verified that all tests pass.
Tested on Kevin, erased the existing NvMem area and verified that TPM
was still manufactured and executed the command: trunks_client --own
Erased parition 0 and 1 in the new locations and repeated the tests.
Change-Id: I295441f94dccdf5a152c32603c2638ffac23f471
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378675
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There is now a call to reset the retry counter before the hard reset
after an update. Cr50 will use the updated image for the next 5 boots,
but on the 6th it sees the retry counter is greater than 5 and then
jumps back to the old image. Cr50 needs to call
system_process_retry_counter to reset the counter and corrupt the old
image header to prevent falling back to the old image.
Normally the reset counter would be processed after it receives a TPM
command. Reef does not have Cr50 TPM support. Until Cr50 has TPM
support for Reef, Cr50 should have a different point to know when the
update is good. This change adds a board property to mark the process
the reset counter once the Cr50 USB controller receives a set address
request from the host. On Reef the controller defaults to the AP PHY
when suzyq is not connected, so it should have a connection to the AP
or through suzyq after boot.
The board property is only added to Reef. Behavior on Kevin and Gru is
unchanged.
BUG=chrome-os-partner:56864
BRANCH=none
TEST=update reef. Wait until Cr50 prints 'SETAD' then run 'rw
0x4000012c' and verify it is reset to 0.
Change-Id: If517202f25a694cd70550e3be047ea502e7c5383
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380354
This patch makes a few small changes to gpio.inc:
- Correct NC1 assignment (GPIO00)
- Add ENG_STRAP (GPIOB6) which is currently not connected to anything.
- Cosmetic fix for LEDs (replace spaces with tabs for alignment)
BUG=none
BRANCH=none
TEST=built and booted on Reef
Change-Id: Ieca83be6c7423694d88f21ebfc3f57849bf42cde
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380449
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This fixes an issue where the power+charge LED sometimes changes
more than once when power is plugged in.
BUG=chrome-os-partner:56471
BRANCH=none
TEST=Reef power+charger LED changes from one color to another instead
of back and forth (unless there are a lot of PD hard resets, but
that's another matter)
Change-Id: I0ea0dd59cbb7c86b758123fd4e6c8e7b20efa5df
Reviewed-on: https://chromium-review.googlesource.com/378756
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Sweetberry specifies UART pins as GPIOs, however
this is not necessary for uart use. Let's remove these.
UART4 is also dup'd with sweetberry's signal gpios, which
is fixed with this CL.
BUG=chromium:608039
TEST=boots
BRANCH=None
Change-Id: I81ee2351c0191ff5ec3d5fad37fe10866bf1ad32
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380439
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change introduces a larger range of tests
for bn_modinv_vartime. The tests are designed
to run on a host, and compare results against
openssl.
BRANCH=none
BUG=chrome-os-partner:47524
TEST=bn_test passes
Change-Id: I2d6ea4824fa82f78f8797c0cfc2cf0dce03e8923
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/365232
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If both e, and MOD are even, then no modular
inverse exists. This change adds handling
for this set of inputs. Adding this change
for completeness (there are no dcrypto library
call paths that generate both e and N as even).
BRANCH=none
BUG=chrome-os-partner:47524
TEST=bn_test passes
Change-Id: Ide64f980501175e9b6078efff92086d12bc1ae2d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/376180
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Before P3 (long time ago), the PI3USB9281 has an I2C requiring a
workaround using the GPIO C15.
The workaround has been removed when we switched to PI3USB9281A
on P3 and the GPIO has been re-used since.
Remove the old GPIO definition to avoid conflicts with its new usage.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:31526
TEST=make BOARD=ryu
Change-Id: Ieb7071b7ca27f3e9a4719592441b6a0b4c455b27
Reviewed-on: https://chromium-review.googlesource.com/380555
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If the firmware was just updated clear the reset counter before
rebooting. This will ensure that the update can complete even if the TPM
isn't being used.
BUG=chrome-os-partner:56864
BRANCH=none
TEST=Set the reset counter to 7 by running 'rw 0x40000128 1' and
'rw 0x4000012c 7'. Then make sure cr50 can still be updated
Change-Id: Ic304fc7a20a4f2af7792f80e970d28e0eb10967e
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380235
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is for boards on which AC_PRESENT can be expected to fluctuate
over a much longer period than the code was originally designed for.
Specifically, USB-PD systems may require several hundred milliseconds
for the state machine to settle before making decisions based on
AC_PRESENT status, for example, changing LED state.
BUG=chrome-os-partner:56471
BRANCH=none
TEST=Tested on Reef with follow-up patch
Change-Id: I370048cb79d1593a14077563ec8db8e8282afb16
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378755
LID_ACCEL_INT_L is a push / pull interrupt pin which is currently unused
by EC FW. Remove the PU to prevent leakage when PP1800_sensor is powered
down.
BUG=chrome-os-partner:56646
BRANCH=None
TEST=On kevin, verify LID_ACCEL_INT_L is consistently logic 0 in S5.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6c748a18bcd183f799b78b4ad9098fff7a7d6567
Reviewed-on: https://chromium-review.googlesource.com/380236
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
SPIP is only used in S0, so keep the module disabled in lower power
states. Disabling SPIP through spi_enable() will also restore our CS pin
to ODR_HIGH.
BUG=chrome-os-partner:56860
BRANCH=None
TEST=Verify SPIP is functional on initial power-up, sysjump, and on
apshutdown / re-power-on. Also verify GPIO_SPI_SENSOR_CS_L goes low in
S5.
Change-Id: I14d845895a43700d2133a532cff63d08f0e64018
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380215
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BC1.2 detection may still occur on multi-purpose ports which we are
currently sourcing. Don't charge from such ports, and don't incorrectly
indicate that external power is present.
BUG=chrome-os-partner:55907
BRANCH=None
TEST=Manual on kevin, plug Apple charge-thru accessory with no charger
attached, verify we don't charge from it.
Change-Id: I9a74f1123fc51c7fc622f985bd528e96b9526946
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378595
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
To support hibernate called from console commands, ectool commands
and key sequence added code to shutdown the AP before hibernating.
BUG=chrome-os-partner:56490
BRANCH=none
TEST=Using console command, ectool command & key sequence verified
both EC and AP are hibernated.
Change-Id: I7708377596d7d4175a44c202ae2385a239ca3d01
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/379157
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The high speed clock does not run when cr50 is in sleep. The low speed
timers do run in sleep and deep sleep. This change modifies the hwtimer
to use the low speed timers instead of the high speed ones.
With this change the system timer frequency is reduced and will only
tick once every 4 mircoseconds. Now the system will resume from sleep
whenever an event is scheduled, but still wont resume from deep sleep.
BUG=chromium:635620
BRANCH=none
TEST=manual
Disable sleep
add a function that prints something every second.
Verify the rollover works at ~4295s.
Change the system time using force_time.
Re-enable sleep and reduce the sleep delays in
board/cr50/board.c and chip/g/idle.ci so cr50 will go to
sleep more quickly. Verify the rollover and changing system
time works.
check that cr50 can go into deep sleep and that the print
statement wont wake it up.
Put the system into deep sleep. Use a wake pin to make it
resume. Verify it can be put back into deep sleep without the
wakepin interrupt constantly triggering.
Change-Id: I70bbc9312cd172661de53334d256949ebab6b5e9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376800
Record what current limit we set when we act as a source
and when we are changing it.
The change should be backward-compatible as older EC will return 0 in
`current_max` when their role is PD_ROLE_SOURCE while newer firmware
will set the actual limit.
BRANCH=none
BUG=chrome-os-partner:56110
TEST=manual: on Kevin, plug and unplug various devices on the 2
ports, and dump the values with 'ectool usbpdpower'.
Change-Id: I8e78663f3196b1b81c2235ed8642da0638bed649
Reviewed-on: https://chromium-review.googlesource.com/375918
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a new source policy to provide 3A if there is only one port used
as a source.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:56110
TEST=manual: on Kevin, plug and unplug various devices on the 2 ports,
while measuring the type-C pull-up with Twinkie.
Change-Id: Ic3dfda7b69d0edeb6b3a9218e723e2c3e0232a51
Reviewed-on: https://chromium-review.googlesource.com/373819
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
CONFIG_POWER_TRACK_HOST_SLEEP_STATE has a dependency on
CONFIG_POWER_COMMON, so remove it from test builds that don't have a
chipset task, rather than heavy-handedly removing it from all test
builds.
BUG=chrome-os-partner:56197
BRANCH=None
TEST=`make BOARD=gru tests`
Change-Id: I86e20b4dccbb01ee285054a47093d6f60abc2166
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378119
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
stm32f446 uses a synopsys designware USB block
rather than the typical ST one. This change adds driver support
for the new block, including usb console support.
BUG=chromium:608039
TEST=usb console works
BRANCH=None
Change-Id: I0e143758ae0b5285f1c94ea2ec5aee159e22e00c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365448
Reviewed-by: Randall Spangler <rspangler@chromium.org>
No need to do set_range in motion_sense_shutdown(), already done at init.
Besides, this is an error if the sensor is not powered in S5.
BUG=b:27849483
BRANCH=cyan, minnie, samus
TEST=Check sensor range is set correctly.
(cherry picked from commit 1018eac30db86dd1d78d5b84b7651edd6aca9225)
Reviewed-on: https://chromium-review.googlesource.com/379097
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Change-Id: Id0b9c2e4988ffc8b55b21258f60b1efa26156dbb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379542
During removing primary power of CPU, EC also needs to handle VW event
of SUS_WARN# in espi driver. Modify the MIWU trigger mode of it from
EDGE_RISING to EDGE_ANYING to solve it.
Modified sources:
1. espi.c: Handling VW event of SUS_WARN# in both edge.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=wheatley; test power sequence on espi POC of wheatley.
Change-Id: I9e45115f3c274d08cdc694911d38599bc8da70c5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/377780
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The SHI lines connected from the EC to the AP and the AP might not be
turned on. We should have a pull down on these lines to avoid them
glitching when the AP is in S3 or S5.
BRANCH=None
BUG=chrome-os-partner:56683
TEST=Verify S3/S5 power is decreased, and SHI interface is still
functional in S0 and on sysjump.
Change-Id: I3a9b018e6e8a5eddb1f23e004f1af3da3e503709
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/376360
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
DUT_HUB_USB_RESET_L was set to input as part of power sequencing
but servod would like to write to it. We'll allow this.
BUG=chromium:571476
TEST=dut-control dut_hub_usb_reset:on
BRANCH=None
Change-Id: I39997e7f7875b833a64f95a1e2ea9434f3523762
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378395
Reviewed-by: Kevin Cheng <kevcheng@chromium.org>
Some target's gcc will detect the address is unaligned and then
expand to byte load sequence, make the address to volatile can
prevent gcc optimize it.
BUG=none
BRANCH=none
TEST=make buildall;
Verified that "crash unaligned" causes a panic on it83xx.
Change-Id: Ieb4f5f8fc65854aefe307fa675fe87d7581452ed
Signed-off-by: Kito Cheng <kito.cheng@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/374281
Reviewed-by: Shawn N <shawnn@chromium.org>
