Add config settings for ODR and EC rate per requestor and
per power state (1 for the AP, 3 for the EC).
This way we can finely set ec rate and ODR depending on usage.
On chromeos, AP is not setting frequency, so EC sets for different power
state. On some platform, sensors can now be suspended in S3/S5.
Allow EC oversampling when AP is only looking for a few samples.
It is useful for double tap detection where high accelerator ODR is
required.
BRANCH=ryu
TEST=Tested on Ryu
BUG=chromium:513458
Change-Id: Ic3888a749699f07b10c5da3bc07204afd4de70da
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295637
Simplify sensor get_data_rate, get_range and get_resolution.
Error code was not checked and these functions as currently implemented
have no reason to fail.
BRANCH=ryu,samus,cyan,strago
BUG=chromium:513458
TEST=Check on ryu, compile
Change-Id: I40dca41cee29a19f65b2f84d434b4c19eb6cbf3c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295635
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
The format of an ep packet header (8 bytes) :
Packets for cc1: [sample_tstamp, sample_seq, vbus_voltage, tstamp_offset]
Packets for cc2: [sample_tstamp, sample_seq, vbus_current, tstamp_offset]
Updated: use array to implement a circular queue; when a forming a packet,
remove one element from the queue. In this way, we can capture more samples
of vbus information.
Updated: when sniffer task has not started sending packets, most recent vbus
info is always stored at the first position of the queue, making sure that
the first reported vbus info is the most recent one.
Updated: allow user to compile the original version or the new version of the
source code. In ec/board/twinkie/board.h
Use #define CONFIG_USBC_SNIFFER_HEADER_V1, if you do not want twinkie to
send out vbus info;
Use #define CONFIG_USBC_SNIFFER_HEADER_V2, if you want twinkie to send out
vbus info.
Signed-off-by: Dawei Li <daweili@google.com>
BUG=chrome-os-partner:42703
BRANCH=none
TEST=BEGIN
connect Twinkie to a waveform generator, record data using:
sudo sigrok-cli -d chromium-twinkie --continuous -o test.sr
then check the resulting waveforms on pulseview.
END
Change-Id: Ifdb6402eb7d998ffb25128c510d1780491b11872
Reviewed-on: https://chromium-review.googlesource.com/282388
Commit-Ready: Sheng-liang Song <ssl@chromium.org>
Tested-by: Dawei Li <daweili@google.com>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Certain boards may need to handle fixing up the RESET_FLAG_s
because of the boards' designs. Provide an optional per-chip
implementation to save the reset flags. Note that this
function is not protected by a CONFIG_ option as it can just
be implemented by the chip if a board requires it. Lastly,
implement chip_save_reset_flags() for mec1322 for future use.
BUG=chrome-os-partner:44527
BRANCH=None
TEST=Built and booted on glados.
Change-Id: I604fe4e6a069f31727bab52288595a349e3dbe72
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295115
Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
AMONBMON is a charger feature to measure input current and battery output
current. ISL9237 output analog value of voltage diff across sense
resistor to EC's ADC channel. This change also reorders oak's ADC channel
to fix a reading bug.
BRANCH=none
BUG=chrome-os-partner:42270
TEST=manual
in EC serial console, type command 'adc' and check AMON_BMON value.
type command 'amonbmon' and check AC current and BAT current.
Change-Id: I9db0a72be7c9a428a16d1609eb8c461c6928e548
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/283665
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a slow inverse matrix calculation function.
It is needed to apply factory offset properly.
Also consider the NULL matrix the identity matrix.
BRANCH=smaug,cyan
TEST=Unit test
BUG=chromium:517675
Change-Id: Ifa11954992e6f2fab02b4e92684e7b01bbaafe94
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294594
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Working on light sensor, sensor were read on every time,
SENSOR_EC_THRES was not taken into account.
Fix 64/32 conversions and add a function for dealing with rollover.
TEST=Set light sensor probe at 1s. Set accel sensor at 100Hz to fill
fifo often; verify that light sensor is queried every second only.
BRANCH=smaug
BUG=chrome-os-partner:39900
Change-Id: If1df53c1a9a304c992f8e517f5d516210118a437
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291992
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add the Silicon Image sensors, add it to the motion_sense module
to be used with the FIFO.
BRANCH=smaug
TEST=Check light and proxy on Smaug:
Check Light value in Lux are reasonable.
Check Proxy is detecting object, but value are in opposite of distance.
BUG=chrome-os-partner:32829
Change-Id: I11419a0f0613f0fae9323f99deedf5a1e6c6e29c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291335
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add a mask of custom events reserved for IRQ based sensors.
Copy data from raw_xzy to xyz while filling the FIFO
when FIFO is enabled.
BRANCH=smaug
TEST=Test with si1141 driver, check irq works for both driver.
BUG=chrome-os-partner:32829
Change-Id: I5e106df0c121e3bf1385f635195717395235ccc3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291334
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Allow sending calibration information to the magnetometer.
BRANCH=smaug
TEST=Check from user space that calibration is taken into account.
BUG=chrome-os-partner:39900
Change-Id: Ic0f595bde1afdc0b6a79e3516a42b55d1f50c17c
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291333
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
PD charger voltage + current can now be limited with
EC_CMD_EXTERNAL_POWER_LIMIT. The limit is automatically cleared when the
AP transitions out of S0 into S3 / suspend.
BUG=chrome-os-partner:43285
TEST=Manual on Samus w/ zinger.
- Plug zinger, verify charging at 20V/3A.
- `ectool extpwrlimit 3000 12000 --dev=1`, verify charging at 12V/3A
- `ectool extpwrlimit 1000 5000 --dev=1`, verify charging at 5V/1A
- Plug zinger into other port, verify still charging at 5V/1A
- `powerd_dbus_suspend`, verify charging at 20V/3A
- `chglim 2000 12000`, verify charging at 12V/2A
- `ectool extpwrlimit 0xffff 0xffff --dev=1`, verify charging at 20V/3A
- `chglim 1000 20000`, verify charging at 20V/1A
- `chglim`, verify charging at 20V/3A
BRANCH=ryu
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6cd5377be91b3df75f99cb414fd3fa5a463b56cb
Reviewed-on: https://chromium-review.googlesource.com/293954
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Some platforms might expect the header of the image to be a certain
platform specific blob. This patch adds an ability to insert an
arbitrary size header in the binary blob, if so desired, the intention
is to have the platform specific tools to postprocess the image and
replace the header with sensible data.
Ideally we should be able to produce an image which is mapped to start
at an offset to the FLASH_BASE, but the macros in ec.S.lds files are
way too smart for this.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with this and other changes the latest cr50 image gets signed and
booted properly.
Change-Id: Icabf00c6b90657b0ae3370ddad3567ccedf3ff49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295200
Reviewed-by: Shawn N <shawnn@chromium.org>
Oak board revisions are not global configs. Move them out of
include/config.h . This change also makes it easier to build EC
and PD image for different board revisions.
BRANCH=none
BUG=none
TEST=manual
build for board revision n and load on oak:
make BOARD=oak clean
make BOARD=oak_pd claen
make EXTRA_CFLAGS=-DBOARD_REV=n BOARD=oak -j
make EXTRA_CFLAGS=-DBOARD_REV=n BOARD=oak_pd -j
Change-Id: I331b4c5a1af94b179d7c6f7878a9c3939ea6025a
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/294441
Reviewed-by: Shawn N <shawnn@chromium.org>
Modified TCPC layer to utilize the Power_Status and Power_Status_Mask
registers. VBUS status is stored in Power_Status and when a change
is detected, it's communicated to the TCPM via the ALERT# line.
BUG=chrome-os-partner:43440
BRANCH=none
TEST=Tested the feature on Glados and Oak connecting to both Ziger
and Samus. Verfied that VBUS status is communicated via the TCPCI and
that PD contracts are established without using the VBUS_WAKE GPIO
lines on Glados and Oak.
Change-Id: Ie5aa32eecc887f3cb00880a285f1e710b7064384
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289931
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
BUG=none
TEST=Used "shutdown -h now" Kernel console command to test on Kunimitsu.
With only battery after 1 hour, device enters to Pseudo G3 and the
V3p3A is off. With AC connected, device is in G3.
BRANCH=none
Change-Id: I955662eb69ac608e9b2d12bdcfbc1258ca83f3a5
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/292976
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create a config to allow customization of a board's charger
termination current and add support to bq2589x charger.
Note, BQ2589X_TERM_CURRENT_LIMIT_DEFAULT, currently set to 64 to make
CL benign to ryu board. Future CL will change to 256 as thats the POR
value for that charger.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42848
TEST=manual, read charger IC register and see its termination current
set to 64mA
Change-Id: I79348ed62a077a6432c8d8db6ac90e1e4e92dbc7
Reviewed-on: https://chromium-review.googlesource.com/293095
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
When there is an interrupt event, N8 CPU will save PSW register to IPSW
register and clear GIE then jump to interrupt service routine. N8 will
restore PSW from IPSW after "iret" instruction (the above are purely
hardware mechanism).
Nested interrupt will occur if we set GIE again in interrupt context.
symptom:
power button pressed while LID open -> exception or unknown reset.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Manually pressed power button x200.
2. Console "eflash" erase and write eflash OK.
Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f
Reviewed-on: https://chromium-review.googlesource.com/289437
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
We will soon have a need to independently set a charge ceiling from both
the PD state machine and from incoming host commands. Store these
ceilings separately, and have the minimum take effect.
BUG=chrome-os-partner:43285
TEST=Pass unit tests. Also, host command current limit takes effect with
subsequent commit.
BRANCH=None
Change-Id: I0ecfe888a7df0d5da5a68999c164c7c841da348b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293818
Reviewed-by: Alec Berg <alecaberg@chromium.org>
TPM command processing should not be happening on the interrupt
context.
This patch adds a skeleton of the task which handles TPM functions. It
initializes the TPM and then enters endless loop waiting for an event
trigger from interrupt, which happens when a valid FIFO message is
received.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=none yet
Change-Id: I63dce2762cc07370a05bf00bdf144c5d9eb6019b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289332
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
`tests` build was previously disabled for glados due to errors building
power/skylake.c. Properly undef the chipset config to make `tests` work
for all skylake platforms.
BUG=None
TEST=`make BOARD=glados tests`
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7a730cdd5e30a932ff0cd1f3beef77873b9e0630
Reviewed-on: https://chromium-review.googlesource.com/292910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new board-level function board_get_gpio_hibernate_state which can
optionally be defined to set the desired state of a GPIO during
hibernate.
BUG=chrome-os-partner:43807
TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console,
verify that LED remains off. Press power button, verify that board wakes.
BRANCH=None
Change-Id: Ica11554e231e88773c3e139fea4622377ebe1e42
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292471
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enabled lid angle calculation. Clamshell/Tablet mode is decided by lid angle.
Accelerometers are set to be active in S3 also.
Trackpad is enabled/disabled by GPIO TP_INT_DISABLE.
Keyboard scan and trackpad are enabled in clamshell mode and disabled in
tablet mode.
Removed enable_keyboard() since keyboard is enabled in clamshell S0 and
S3.
BUG=chrome-os-partner:41353
TEST=Verify in clamshell mode, system can be waken up from S3 by keyboard/trackpad;
And not tablet mode.
BRANCH=None
Change-Id: Ic5fb5a562e8426288eae2fb9815a213fe5033955
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/287341
Reviewed-by: Shawn N <shawnn@chromium.org>
Early hardware bringup often is complicated by exceptions happening in
the code all over the place. Using interrupt based console output to
trace startup progress is inefficient - a lot of text gets buffered
and never shows up on the console.
The new config option enables the mode where the console output is
supposed to be happening in polling mode, the character transmit
function not exiting until the entire character is transmitted.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=with the new config enabled (and the appropriate changes to
chip/g/uart.c) was able to debug bringup on the new version.
Change-Id: I85fd2f3990ac1d31097d58bd6a7fa658b2b5146e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/291852
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Now that v3 support is in the cros_ec kernel driver and depthcharge,
deprecate support for the old v2 protocol. At some point in the future,
support for the v2 protocol will dropped entirely.
Boards that require support for the V2 protocol should enable the
following config option.
#define CONFIG_SPI_PROTOCOL_V2
BUG=chrome-os-partner:20533
BRANCH=None
TEST=make -j buildall tests
TEST=Flash jerry, AP & EC boot successful.
TEST=`ectool protoinfo` shows only version 3 supported on jerry.
TEST=Flashrom still works on jerry.
Change-Id: I72d3aee00879314b936cc0b1002c9883550b1f1a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/291411
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Move common USB charger code out of board directory including
setting VBUS supplier when VBUS changes, and initializing BC1.2
supplier types on init.
This also enables re-enabling of Pericom BC1.2 detection interrupts
when VBUS is changed on all boards that use USB_CHG task.
BUG=chrome-os-partner:42292
BRANCH=none
TEST=make -j buildall. Tested on glados and samus by plugging in
a few different chargers and making sure we charge.
Change-Id: Ib102fbf7a6aace998e6fcb6d35f3c97e5f03f5c2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290453
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Add support for ADC / thermistor reads on the BD99992GW PMIC.
BUG=chrome-os-partner:42156
TEST=Manual on Glados with subsequent commit. Boot to S0, run "temps".
Verify that temperatures start around 28C and begin to increase after
system is powered-on for a long duration.
BRANCH=None
Change-Id: Ic15f41046130317a0e0c3bce4a923ba624328c0d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289935
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Don't enable try.src when battery is not present or <1% because
try.src will temporarily cut off power to system.
BUG=chrome-os-partner:43413
BRANCH=samus
TEST=tested on samus using "battfake" ec command. when battery
<1%, verified that try.src is disabled and when battery >=1% and
the AP is on (dual-role toggling is on), then try.src is enabled.
verified boot without battery succeeds on samus and glados.
Change-Id: I64816bb7c9669bfeca61687bcd9a48da32e67945
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289854
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When LPC mode is used, there is an assumption that the first
2 sensors are accelerometers, and the optional 3rd is a gyro.
Put the code that fill lpc_data with #ifdef.
Prevent lpc space corruption if more than 3 sensors are present.
BRANCH=smaug
TEST=Compile. Smaug works
BUG=None
Change-Id: I12c9b823efb57d7b190a1813228f6f02fa0bebcb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290073
Add interface to access the sensor using SPI interface.
BRANCH=smaug
TEST=compile and work on new Ryu board
BUG=chrome-os-partner:42304
Change-Id: I987259a7e378de8ada3b3b55b3662e5028ea31b2
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288515
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
Added macros to conditionally compile the console commands to save the
memory. These macros can be enabled/disabled in the board specific files.
BUG=none
TEST=make buildall -j
BRANCH=none
Change-Id: I108a072c333762cd24ea973612202c9cc4d40914
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/288950
Reviewed-by: Shawn N <shawnn@chromium.org>
Modify host_command_pd.c to loop over sending of PD status
host command and processing the response as long as the
alert GPIO is active.
This fixes a potential bug that if the alert line is held
low for more than one PD status host command, then we would
not process the return status.
Also, fix a bug in which we could call alert() for a
non-existent port.
BUG=none
BRANCH=strago
TEST=verified on samus and glados. connected charger and verified
that we negotiate a contract and set appropriate input currnet limit.
Change-Id: I3b2db87b51f55fc2b20a4695bd466ff8bb09ea55
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288819
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: David James <davidjames@chromium.org>
For multi-byte ACPI memmap reads, we previously had a mutex to ensure
data continuity. A better approach is to use a read cache. Since the
kernel will enable burst mode before reading a multi-byte memmap
variable and disable it afterward, we can populate the cache on the
first read after enabling burst. This solution removes deadlock bugs, is
contained entirely in acpi.c, and saves a deferred function.
BUG=chromium:514283
TEST=Manual on Glados. Add prints in acpi_read, verify that multi-byte
reads come from cache and non-burst reads continue to function as
before.
BRANCH=Cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74e4927bf2b433e31a9ff65d72820fa087c51722
Reviewed-on: https://chromium-review.googlesource.com/288871
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
active state is global, remove it from motion_sensor structure.
Reinit sensors when entering RW, fix regression introduced by CL:284616.
Improve EC polling rate calculation by excluding suspended sensors.
Wake up sensor thread in case the motion task was in deep sleep.
Do not send sense interrupt while suspened. Will revisit once wakeup
sensors are implemented.
BRANCH=smaug
TEST=Check when in RW the sensors are exposed.
Check EC rate are correct in different power state.
Check when jumping from RO to RW and back, after setting the
frequencies parameters via sysfs properly, AndroSensor acquires
the data properly.
BUG=chrome-os-partner:43132,chrome-os-partner:40741
Change-Id: Ie70732b135a432d64935eead4200ddc0e1a7c0b4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288201
Reviewed-by: Alec Berg <alecaberg@chromium.org>
After I2C unwedge, *all* I2C ports will be re-initialized in
i2c_raw_mode() by gpio_config_module(MODULE_I2C, 1);
This means *all* I2C pins will be programmed as GPIO then enable I2C
alternate function.
If I2C Unwedge happened while there is an active I2C transacation on
another port, the active I2C transaction will be corrupted, since the
pins will be temporary programmed as GPIO Output High.
BUG=chrome-os-partner:40519
TEST=Warm-reboot test on Cyan EVT and no discharging while AC is on.
BRANCH=none
Change-Id: I3be1d5c60bf4ab385bc077202406ec7abd8b2add
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/287493
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Denny Iriawan <denny.iriawan@intel.com>
This patch adds a module which runs on top of the SPS driver and
implements the TCG SPI TPM protocol.
Basic register read and write functions are implemented as well as
rudimentary TPM state machine (claiming/releasing locality).
An enhancement is made to the SPS driver to ensure that when the CS is
deasserted the transmit FIFO is reset too, on the off chance of the CS
going away mid transaction for whatever reason.
In this implementation the slave is guaranteed to stall the master for
a few bytes in both receive and transmit transactions, which is
further aggravated by the fact that RX FIFO threshold is set to 8
(this is the minimum number of bytes the master has to send to wake up
the slave). This could be fine tuned later, for instance made a
parameter of the receive callback registration function.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=trunksd initialization (with minor changes to accommodate new
VID/DID and some status bits, to be published) succeeds with the
cr50 connected to the USB/SPI cable.
Change-Id: I28d37c3b57dde9adf59e81426efe4f58880cf0b0
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285252
As new features come along the console channel space limited at 32
becomes very tight. But not all features are present all the time.
Let's make some of the channels compile time configurable. This makes
for uglier code but allows to support more channels.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Id21560d4aa05c0e5245872c50ae19340cda8fd3e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286610
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
SPI slave and master interfaces require very different code to
support, they should have separate configuration options.
Host command code printouts should use their own console channel.
Using SPS to designate SPI Slave interface is not universally
acceptable, a bug has been opened to discuss the alternatives and
clean up the code.
BRANCH=none
BUG=chromium:512613
TEST=make buildall -j
Change-Id: I6683286a221c4689ecc247fdfe8ebca529f3f458
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286469
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add a X-macro CONFIG_LID_SWITCH_GPIO_LIST to be able to optionally
specify more than one GPIO to check to find out whether the lid is open.
By default, use GPIO_LID_OPEN as before.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42110
TEST=on Smaug EVT2, define CONFIG_LID_SWITCH_GPIO_LIST as
LID_GPIO(GPIO_LID_OPEN) LID_GPIO(GPIO_BASE_PRES_L) and play with magnets
and the genuine lid, check we get the right "lid open" / "lid close"
messages on the console.
Change-Id: I9e7c67bb39f36f254d31d5861d535d69db754faa
Reviewed-on: https://chromium-review.googlesource.com/287852
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
