This is the recommended futility signature type for new boards.
BRANCH=none
BUG=chromium:690773
TEST=Flash hammer, RW image checked correctly
TEST=futility show --type rwsig \
--pubkey build/hammer/key.vbpubk2 build/hammer/ec.RW.bin
Change-Id: Id8648199891fdd4df63ecb599e0c5e927bc861d0
Reviewed-on: https://chromium-review.googlesource.com/441549
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The code deciding which partition to choose properly determines which
one is newer, but invariably populates the cache with the second one,
when both partitions are valid.
This is obviously wrong, on top of that there is no need to check both
partitions' validity, if the newer one checks out.
BRANCH=none
BUG=chrome-os-partner:60555, chrome-os-partner:61972
BUG=chrome-os-partner:61716, chrome-os-partner:61234
BUG=chrome-os-partner:61167, chrome-os-partner:60555
TEST=successfully ran
$ ssh 192.168.1.102 suspend_stress_test --suspend_min 10 \
--suspend_max 10 --wake_max 10 --wake_min 10
for more than 300 cycles (it still is going)
Change-Id: I02d9bb062b9edbbb9787a95ba760872e09ff2761
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Current code puts key at the end of the first half of flash, which
may not match the actual RO section size (e.g., it might be PSTATE,
not RO). This makes sure the key to be at the end of RO section, and
signature at the end of RW section, no matter the actual layout
being used.
However, the (deprecated) usbpd1 image type assumes that flash is
equally split between RO and RW, so we do not change that.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make BOARD=hammer -j && deploy
TEST=make BOARD=hoho -j && \
futility show --type usbpd1 build/hoho/ec.bin
Change-Id: Ia02e927f9128d6ec3d0b780c28312e0d18835d72
Reviewed-on: https://chromium-review.googlesource.com/426100
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Presently the CR50_DEV make variable is loaded: it enables debug
extensions in the produced cr50 image AND requires that the image is
signed with the key from the signing fob.
In fact these are two independent requirements: it is possible to use
an image built with CR50_DEV set for a dev H1 which does not require
fob signing.
A proper indication of the need to use the signing fob would be the
fact that H1_DEVIDS is defined, as it means a that node locked image
is being produced.
Images built without H1_DEVIDS set can be used on H1s which run with
the dev RO and as such do not need to be node locked, they are
signed with a well known key from util/signer/loader-testkey-A.pem.
This patch also tweaks passing the H1_DEVIDS variable to the shell
when altering the manifest. Without this tweak H1_DEVIDS definition as
make command line argument (as opposed to environment variable) was
not making it into the subshell invoked by make.
BRANCH=none
BUG=chrome-os-partner:62457
TEST=ran the following:
- built cr50 images with H1_DEVIDS defined in the environment and
in the command line, observed that the properly signed prod
image is produced (boots on a prod H1 in node locked mode).
- verified that adding CR50_DEV=1 to H1_DEVIDS in either
environment or the command line produces a properly signed
DEV image.
- verified that specifying CR50_DEV=1 alone in either environment
of command line produces a DEV image which does not require fob
signing.
Change-Id: Ied65a0bc50926aa5b6fa65e51805c2368522dcf2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434926
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Cr50 on x86 will run normally enter deep sleep and then wake up
immediately. When the AP turns off it stops pulling up the i2cs signals.
When cr50 enters deep sleep it sees that the i2cs signals are low then
wakes up immediately. After resuming cr50 will remain awake for 20 then
enter deep sleep. At this point it will remain asleep.
This change disables i2cs_sda and scl as wake pins when entering deep
sleep. Just like ARM these tpm signals are not in use when the device is
off. We have other signals to detect when the system leaves s3 or s5, so
we should rely on those.
We need this change because we want cr50 to fully enter deep sleep when
we run suspend resume tests. Right now the AP does not sleep long enough
for cr50 to enter the second deep sleep.
BUG=none
BRANCH=none
TEST=turn off the AP and make sure cr50 doesn't resume from deep sleep
immediately. run suspend_stress_test -c 5000 and verify cr50 enters deep
sleep and resumes correctly. verify dioa9 and dioa1 are enabled as wake
pins on resume
Change-Id: Ided8b2b7d5455650bca1e8d781063d092fb74c43
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443389
Added interrupt handler for CABLE_DET signal on both port 0/1. This
allows us to define CONFIG_USB_PD_TCPC_LOW_POWER.
BUG=chrome-os-partner:63067
BRANCH=none
TEST=Connected USB mouse, keyboard and USB stick to both ports and
verified the devices were recognized and attached properly. Verified
that ports 0/1 always worked with blackcat typeC charger.
Change-Id: I4d8a8bdba4f95e73333e2e01f11fe1d48453a2fe
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444315
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Added Si114x light sensor to the motion sense struct and enabled it in
polling mode. Also added backward compatibility for the ALS to report
readings via ACPI.
BUG=chrome-os-partner:61470
BRANCH=none
TEST=Enter 'accelinfo on 1000' on the EC console and verify light
readings are present and they increase/decrease as the light pointed
to the sensor changes. Also verifed with AIDA64 app in arc++
Change-Id: I22e0b87034150d2e987987da053de3c312fcc98b
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440378
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Eve P1 is missing the ALS_INT_L signal and so needs to poll the
Si114x. This CL adds a new config option CONFIG_ALS_SI114X_POLLING
that when defined uses a deferred callback to trigger the motion
sensor event that reads sensor registers. The deferred callback uses a
8 msec delay which is ~2x longer than the time required by the sensor
to complete the measurement.
BUG=chrome-os-partner:61470
BRANCH=none
TEST=On Eve verify that light sensor measurments are present with the
'accelinfo on 1000' command.
Change-Id: I212bebf2ceacbac87ccb0734cc4990dbc349b028
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440377
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The USB FW upgrade endpoint should really only accept vendor commands
required to perform the firmware update. This commit adds a whitelist
that is checked whenever a vendor command is received over this
endpoint.
The allowed commands over USB are the following:
- EXTENSION_POST_RESET
- VENDOR_CC_IMMEDIATE_RESET (only for dev images)
There is also functionality to have a whitelist for vendor commands that
come over the TPM interface.
BUG=chrome-os-partner:62815
BRANCH=None
TEST=Flash Cr50 with image containing this change. Verify that an
upgrade over USB to newer image works.
TEST=Try using usb_updater to send a vendor command that's not in the
whitelist. Verify that the vendor command is dropped.
Change-Id: I71f8ba090a1cc6c9e7c30ce0dd3c25259e8f292f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443447
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Currently, manually triggered reboots cause the retry counter to be
incremented. However, if the system is responsive enough to process the
reboot commands from either the console or TPM vendor command, we can
assume that the image is "ok". This commit changes the Cr50 behaviour
to decrement the retry counter when a reboot is issued on the console or
the TPM vendor command is received.
BUG=chrome-os-partner:62687
BRANCH=None
TEST=Flash cr50. Flash an older image in the other slot. Enter the
reboot command on the console over 10 times and verify that retry
counter never exceeds RW_BOOT_MAX_RETRY_COUNT and older image is never
executed.
CQ-DEPEND=CL:444264
Change-Id: Ic35bdc63c4141834584a00a7ecceab2abe8dfc21
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/443330
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In chipset_handle_espi_reset_assert, check the state of SLP_SUS# signal
using power_get_signals instead of power_has_signals since we do not
care if the check fails. This avoids unwanted "power lost input" prints
on the EC console.
BUG=chrome-os-partner:63033
BRANCH=None
TEST=Verified that entry into S3 does not result in any "power lost
input" messages on EC console.
Change-Id: I88bc76a90b48e7c565423235f6e8431176ed4872
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444262
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The matrix was not correct and sensor would report -1G along the Z axis
while on a flat surface.
BUG=chrome-os-partner:63021
BRANCH=none
TEST=Check in ARC++ AIDA64 the gravity data is reported correctly along
the Z axis.
Change-Id: I0ddbf40876746432c640f547a5efede3a07c6eec
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444066
Tested-by: Rajat Jain <rajatja@chromium.org>
Reviewed-by: Rajat Jain <rajatja@chromium.org>
As the new form-factor has the lid accelerometer on the
reversed side facing the B-cover, the matrix setting
depending on board version; in such matter, it should be
able to compatible with old version of boards.
We create a new hook function for board specific tweaks,
this is because since the commit of 0c57824
("reef: Re-factor PP5000 and PP3300 enable/disable"),
the board_init() is no longer a good place for tweaks,
because ADC read should come after adc_init();
such that, new hook ensures robust ADC reading which is
the source of board version.
Also, we fix an arithmetic error for version-3 workaround,
i.e. patch the commit of ca99f38 ("snappy: BMI160 is
powered down on board v3 and older in S3"), else it could
trigger unexpected EC panic like this:
[89.770776 chipset -> S3]
[89.771222 power state 2 = S3, in 0x006d]
[89.772428 I2C unwedge failed, SCL is being held low]
[89.773775 TCPC p0 Low Power Mode]
[89.812962 Reset i2c 01 fail!]
...snip...
[91.816415 Unexpected i2c state machine! 1]
Time: 0x00000000057a7d9c us, 91.913628 s
Deadline: 0x00000000057a8a1d -> 0.003201 s from now
...snip...
Rebooting...
--- UART initialized after reboot ---
[Reset cause: soft]
...snip...
BUG=chrome-os-partner:62676
BRANCH=reef
TEST=check the DVT1 and DVT2 unit rotate normally.
Change-Id: Ic53e67e0c97e57056587adb6b260e81c0f99437a
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/442252
Commit-Ready: Chen Wisley <wisley.chen@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Harry Pan <harry.pan@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Saying that 'flashwp rw' was protecting RW region was not really
accurate: it was actually protecting the whole flash (which,
well, is actually equivalent as the RW can't be protected without
the RO).
Let's fix that in anticipation for adding a new flag that will
_really_ set the RW protection (and only that).
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make buildall -j
Change-Id: Ic1c585622330b4976e71150f3a71b74a031a7694
Reviewed-on: https://chromium-review.googlesource.com/442264
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
usbpd1 futility image type is deprecated and should not be used for
new designs. This adds proper support for rwsig image type.
Key and signatures are added at linker stage step (futility cannot
directly create such signed images). Thanks to VB21 header, rwsig.c
can now tell how many bytes of the RW image need to be
cryptographically verified, and ensure that the rest is blank (0xff).
BRANCH=none
BUG=chromium:690773
TEST=make BOARD=hammer; flash, RW image is verified correctly.
TEST=make runtests -j
TEST=For the rest of the tests:
Change config option to CONFIG_RWSIG_TYPE_RWSIG
TEST=make BOARD=hammer; flash, hammer still verifies correctly.
TEST=cp build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig;
futility sign --type rwsig --prikey build/hammer/key.vbprik2 \
build/hammer/ec.RW.bin
diff build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig
=> Same file
TEST=Add CONFIG_CMD_FLASH, flashwrite 0x1e000, reboot, EC does
not verify anymore.
TEST=dump_fmap build/hammer/ec.bin shows KEY_RO and SIG_RW at
correct locations.
Change-Id: I50ec828284c2d1eca67fa8cbddaf6f3b06606c82
Reviewed-on: https://chromium-review.googlesource.com/441546
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable CONFIG_USB_PD_TCPC_LOW_POWER, and add cable detection handling.
BRANCH=none
BUG=chrome-os-partner:62964
TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter:
keyboard works; charging works
Change-Id: I0751cc7b5fc8ba71388f08b7001c0daceda37bb6
Reviewed-on: https://chromium-review.googlesource.com/443747
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit 18327455c1 ("ANX74xx: add TCPC low power mode for different
DRP state") introduced new code to put ANX74xx in low power mode.
However, this broke existing boards that do not enable
CONFIG_USB_PD_TCPC_LOW_POWER (and therefore do not implement cable
detection interrupt).
BUG=chrome-os-partner:59841, chrome-os-partner:61640
BUG=chrome-os-partner:62964
BRANCH=none
TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter:
keyboard works
Change-Id: I4b66511b816afee402a7e769aa6d2c323724d071
Reviewed-on: https://chromium-review.googlesource.com/443865
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Should be close to the STM32L476 in the STM32L4 family.
Slightly different flash/RAM.
It's currently running from the internal clock (HSI) at 16Mhz,
we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us
the PLL locking time).
The internal flash write/erase/protection is still not implemented for
the whole STM32L4 family.
Upgrade the SPI master support and verify that the TX works.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=make BOARD=eve_fp
run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES)
Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e
Reviewed-on: https://chromium-review.googlesource.com/442466
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Use the motion sensor to manage ALS as well.
The current interface (via memmap) is preserved, but
we can also access the sensor via cros ec sensor stack and
send the ALS information to ARC++.
BUG=chrome-os-partner:59423
BRANCH=reef
CQ-DEPEND=CL:424217
TEST=Check the sensor is working via ACPI sensor and
cros ec sensor. Check ARC++ sees the sensors.
Change-Id: Iaf608370454ad582691b72b471ea87b511863a78
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424323
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There are two batteries being evaludated for Eve and there needs to be
a batteery_info struct for each one for situations where the gas gauge
can't be read and the charge state machine uses these parameters.
BUG=chrome-os-partner:62711
BRANCH=none
TEST=Verifed that battery_type is read correctly for both LG and
LISHEN battery units.
On Lishen unit Drain battery completely, then reconnect type C
charger. Verified that battery is now charging. Prior to this CL, the
LISHEN bat would not charge because the internal overcurrent protection
mode would not tolerate the 256 mA precharge current that's specified
for the LG battery.
Tested that both Lishen and LG recovered after forcing a battery
disconnect.
Change-Id: I201eaf61ad03d3dc0d199ab441b07c371bceddde
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440514
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This change adds an option to pdchipinfo command to force ec to get
the version from the chip instead of the cache (if it's available).
This option will be used after firmware update, which makes the cache
value stale.
BUG=chrome-os-partner:62383
BRANCH=none
TEST=Run ectool as follows:
localhost ~ # /tmp/ectool pdchipinfo 0 on
vendor_id: 0xaaaa
product_id: 0x3429
device_id: 0xad
fw_version: 0x15
localhost ~ # /tmp/ectool pdchipinfo 1 on
EC result 2 (ERROR)
Change-Id: Icefe96d7fc1208b991a4caa13aaf4f04052edba7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441271
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The firmware version formats may vary chip to chip. fw_version field is
changed to a union of a 8 byte string and an 64-bit integer.
BUG=chrome-os-partner:62383
BRANCH=none
TEST=ectool pdchipinfo 0/1 on Electro
Change-Id: Id51e66c44338a09ed897ee61f54cd6a394400e63
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441270
With this change, only DEV images will have the capability to unlock the
Cr50 console.
BUG=chrome-os-partner:62727
BRANCH=None
TEST=Build a prod image, flash Cr50, try to unlock the console. Verify
that access is denied and console remains locked.
TEST=Attempt to read EC and AP flash over ccd. Verify that it fails.
TEST=Remove AC and battery. Plug in AC. Verify that console is still
locked.
TEST=Plug in AC, unplug battery, verify that write protect is disabled.
Verify that console is still locked and cannot be unlocked.
TEST=Build a dev image, verify that console can be locked and unlocked.
Change-Id: Ic47aa34f42ee295e74ba3a40b709ac42c34a30b7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439764
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Make FIFO a stack variable to save static memory,
Remove auto_inc argument, always set
Remove constant for rate 0.
Force board to declare sensor private data.
Avoid name collision in stm_mems_common
Include stm_mems_common.h in accel_lis2dh.h, caller only need to
include accel_lis2dh.h.
BUG=none
BRANCH=none
TEST=Compile with discovery_stmems board.
Change-Id: Id52b54dd4ec3cf217247c5511ad5a506067ad293
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441144
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: mario tesi <mario.tesi@st.com>
The trackpad interrupt is input only to the EC and should not ever
be driven from here.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build and boot on eve p1
Change-Id: I3ffa2ddb4990550b57c9191b5d721ab0ba206aca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439829
In preparation for adding the rollback protection block, pass
EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot,
instead of an enumeration no protection/RO/ALL.
This will later allow us to protect/unprotect the rollback region only,
by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection
can be checked with flasherase/flashwrite.
TEST=On hammer (stm32f072):
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp rw; reboot => RO+RW protected
flashwp norw; reboot => only RO protected
TEST=On reef (npcx):
deassert WP, flashwp false; flashinfo => RO+RW not protected
flashwp true => only RO protected
reboot => only RO protected
flashwp rw => RO+RW protected
reboot => only RO protected
Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f
Reviewed-on: https://chromium-review.googlesource.com/430518
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Poppy uses SPI, Plt_Rst, and USB to AP. Its strapping option is 1M PU
on both DIOA9|DIOA1 which gives it a strap_config value of 0xA.
Rowan uses I2C and it's strapping option is 5k PD on DI0A12 and 5k PU
on DI0A6 which gives it a strap_config value of 0x30.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Used H1 dev board with external PU/PD resistors to replicate both the
Poppy and Rowan configurations.
With Poppy config console shows:
[0.004468 Valid strap: 0xa properties: 0x45]
With Rowan config console shows:
[0.004460 Valid strap: 0x30 properties: 0x2]
Change-Id: I569960114c6f1844a55912fbf7f3d97008f9f71f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428000
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
When --raiden is passed as a command line parameter, do not proceed
programming as if it were not present, alert the user and refuse to
proceed instead.
Need to jump though a couple of extra hoops to avoid printing the
error message twice.
BRANCH=none
BUG=none
TEST=tried running with boards supporting and not supporting
programming over CCD.
$ ./util/flash_ec --board=oak --raiden --image rowan.ec.bin
INFO: Using ec image : rowan.ec.bin
ERROR: raiden mode not supported on oak
$ ./util/flash_ec --board=kevin --raiden --image rowan.ec.bin
INFO: Using ec image : rowan.ec.bin
INFO: Flashing chip npcx_spi.
INFO: Using raiden debug cable.
...
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ia40f348e6dde57fc2f4c49719bc2a0947036dcc1
Reviewed-on: https://chromium-review.googlesource.com/440051
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This removes CONFIG_USB_PD_TCPC_FW_VERSION.
board_print_tcpc_fw_version is removed since it's no longer called.
PD chip info is printed in usb_pd_protocol.c.
BUG=none
BRANCH=none
TEST=buildall. Boot Electro, verify chip info is printed.
Change-Id: I2ff860c2a1b17ceea124644ba8feb356b9cca2eb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434911
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added code to put the ANX74xx in low power mode for different DRP state.
1. When nothing attached or system is in S3 or S5 disable the auto
toggling and put ANX74xx system in Analog control mode.
2. Using the CABLE_DET interrupt pin (attach event) enable normal power
mode.
BUG=chrome-os-partner:59841, chrome-os-partner:61640
BRANCH=None
TEST=Manually tested on Reef using below dut-control command
dut-control pp3300_pd_a_mw -r <n>
1. S0, S3, S5 - Nothing connected, ANX in low power mode.
2. In S0 SNK (display/USB dongle, eMark cable) connected & put
system to S3, ANX remains in normal mode.
3. In S0 SNK connected & put system to S5, ANX in low power** mode.
4. In S0 nothing connected, put system to S3 or S5, attach
SNK, ANX in low power** mode.
5. Attach SNK at S3/S5 & boot to S0, ANX in normal mode.
6. SRC (AC adapter) with/without eMark cable are detected in
S0, S3, S5, and continue to charge the system after S-state
transition.
low power**: ANX74xx hardware limitation that Ra/Open (Ex: E-Mark cable
only) detection will trigger CABLE_DET continuously, therefore ANX74xx
will go to normal power mode momentarily and then low power mode in a
loop.
Change-Id: I30f7fd7a85e31987fb77e2cab2fe140d59dd3629
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/415580
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Shorten certain long prints and reduce the precision of timestamp prints
when CONFIG_CONSOLE_VERBOSE is undef'd.
BUG=chromium:688743
BRANCH=gru
TEST=On kevin, cold reset the EC, boot to OS, and verify cros_ec.log
contains all data since sysjump and is < 2K bytes (~1500 bytes).
Change-Id: Ia9390867788d0ab3087f827b0296107b4e9d4bca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438932
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If PD is negotiated and the EC is reset, a source partner port will
continue providing its negotiated voltage (eg. 20V in the case of
zinger). Ensure the partner port is in a known state by providing Rp
for a brief period after resetting to RO.
BUG=chrome-os-partner:62281
BRANCH=Reef
TEST=On kevin, attach zinger, wait for 20V negotiation, and press F3 +
power to cause EC reset. Verify VBUS drops to approximately 0V before
going back to 5V / 20V. Verify the same with kevin OEM charger as well.
Also verify kevin boots with no battery.
Change-Id: I1b769a76188d8a9a515388996fbc4cb3d46840a5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433367
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Electro is able to boot on 15w to Depthcharge but requires 18w or above
to boot to the logon screen. This patch allows 15w charger to boot
Electro to Depthcharge (as before) but prevents it from booting after
that unless the EC in RW negotiates with the charger and gets 18w or
more.
Without the patch:
1. Boot without battery
2. EC sysjumps to RW
3.a. With 18w charger, Depthcharge proceeds to boot
b. With 15w charger, Depthcharge proceeds then browns out
4. Boot without battery
5. Reboot by FSP for RTC well drop
6. Charger goes to disabled state
7. EC fails to negotiate with charger, hard resets charger
8. Brownout
9. Repeat from #4
With the patch:
1. Boot without battery
2. EC sysjumps to RW
3.a. With 18w charger, Depthcharge proceeds to boot
b. With 15w charger, Depthcharge times out and shuts down the system
So, the outcome is same. With the patch, the user at least is (or will
be) given a chance to know battery is the problem. I suppose we have to
add a screen showing battery is drained or dead. I currently see no
such code in vboot_select_and_load_kernel.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=chrome-os-partner:61801
BRANCH=none
TEST=Hack the code to enforce syslock. Disconnect battery.
Use 18w charger to boot the system. Use 15w charger not to boot.
Change-Id: I00d79a96221f1d3b8c6d529de9b8e4588d6112aa
Reviewed-on: https://chromium-review.googlesource.com/440390
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
