To implement rtc driver for some ec chips, we
need to convert between calandar date and seconds
(since epoch time, 01-01-1970 00:00:00).
Sicne these functions are HW-independent, let's add
common/rtc.c, include/rtc.h, and unit test for this.
BUG=b:63908519
BRANCH=none
TEST=make buildall test -j
Change-Id: Icb1e768d2b3674d5225b83e09475e984eb104d06
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/666985
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
This change is required to reboot the chip without bringing down the
entire platform on boards where GPIOs are wired to external active reset
signals.
BRANCH=none
BUG=none
TEST=Scoped a pin across a reset.
Change-Id: I58d93697d39a8adcdac9324d5dd9da00745aec9a
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/644179
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When compilation is enabled, this function prints all prime numbers
generated using the PRIME_DELTAS array.
BRANCH=cr50
BUG=none
TEST=verified that prime numbers are printed out when running rsa_test.py
Change-Id: I37961aad146c4aeecca9a84550f313450e6c5853
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683074
Reviewed-by: Shawn N <shawnn@chromium.org>
The TPM test directory has bitrotted and does not compile any more,
leave alone pass tests. This patch updates the tests to match changed
EC codebase:
test/tpm_test/Makefile - look for include files in more directories
test/tpm_test/bn_test.c - add implementation of always_memset() which
for the EC tree now comes from a different tree and provide a plug
for watchdog_reload() which is no used by dcrypto code (which in
fact is not a good idea, but an issue for another day).
test/tpm_test/hash_test.py - update to match new format of return messages
test/tpm_test/upgrade_test.py - update to match the new format of
return messages and limit the test to installing just 2K worth of
data
BRANCH=cr50
BUG=none
TEST=./test/tpmtest/tpmtest.py now passes
Change-Id: Ibcd7fcfba06cd83023e35a2ac4f37ec896492ad4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665322
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The hash test code memory management is somewhat loose: it does not
clean up allocated buffer, but then uses it to check for presence of
the previously created handles, which can result in false positives.
Let's zero the buffer each time it is allocated and let's use
hash_test_db.contexts as the indicator if the buffer is allocated or
not.
BRANCH=cr50
BUG=none
TEST=ran ./test/tpm_test/tpmtest.py, observed rsa tests pass.
Change-Id: Iad4b4e2662fc7266ee6f556f6ddfd0051e7172d7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665321
Reviewed-by: Shawn N <shawnn@chromium.org>
Based on measurements, Samus can pull more current than desired, even
taking into account the existing INPUT_CURRENT_LIMIT_OFFSET_MA
adjustment. Decrease the programmed current limit by an additional
factor, determined by taking the worst-case power measurements across 15
different Samus devices, to ensure that Samus never pulls more current
than desired.
BUG=chrome-os-partner:55297
BRANCH=samus
TEST=Verify with debug prints that curr_lim_ma becomes 256 when
negotiated current limit is 500mA and curr_lim_ma becomes 2556 when
negotiated limit is 3000mA.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6912d987c5a519f55a831698873a69c4cac817b8
Reviewed-on: https://chromium-review.googlesource.com/684696
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Trigger the power press for shutdown. Also, avoid powering up the AP
by checking if we are not in G3, before triggering the power press.
BUG=b:66698593
TEST=
> apshutdown
[7045.198370 chipset_force_shutdown()]
[7045.198870 PB PCH force press]
[7045.199368 PB PCH pwrbtn=LOW]
> LPC RESET# asserted[7049.218062 power state 3 = S0, in 0x000c]
[7049.218718 Pass through VGATE: 0]
[7049.219281 power state 7 = S0->S3, in 0x000c]
[7049.220647 chipset -> S3]
[7049.221108 power state 2 = S3, in 0x000c]
[7049.221763 power state 8 = S3->S5, in 0x000c]
[7049.222522 USB charge p0 m0]
[7049.223217 chipset -> S5]
[7049.223716 power state 1 = S5, in 0x000c]
[7049.224334 PB PCH force release]
[7049.224840 PB PCH pwrbtn=HIGH]
[7049.232875 SW 0x01]
[7049.240557 TCPC p1 Low Power Mode]
[7049.252249 TCPC p1 Low Power Mode]
[7049.254363 TCPC p0 Low Power Mode]
[7049.266006 TCPC p0 Low Power Mode]
[7059.225553 power state 9 = S5->G3, in 0x000c]
[7059.226188 chipset_force_shutdown()]
[7059.226717 PB PCH force press]
[7059.233871 PB PCH pwrbtn=LOW]
[7059.234381 power state 0 = G3, in 0x000c]
[7059.250255 power state 0 = G3, in 0x000f]
[7059.256533 SW 0x05]
Change-Id: Ibc27c90f806deed6a2ca7035869c4e10ca7fbf0b
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://chromium-review.googlesource.com/683956
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently we are assuming batt_mode would never be zero, but that is not
always true. Some battery do report zero for batt_mode(bob for example).
So everytime the batt_mode_cache been set to zero, the virtual_battery
would consider it uninited, and tries to refresh the next time.
Use -1 as uninited batt_mode_cache to avoid that.
BUG=b:66555246
BRANCH=gru
TEST=Check on bob, the battery level is correct.
Change-Id: Ieb7ec9403f69a6b5bca93c6682ec6117fe95fe1e
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/678135
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Fizz has an over current control system. There are two FETs
connected to two registers: PR257 & PR258. They control
the max input current as follows:
PR257, PR258
For 4.62A (90W BJ adapter), on, off
For 3.33A (65W BJ adapter), off, on
For 3.00A (Type-C adapter), off, off
BJ adapters are distinguished by reading GPIO71.
This patch also removes ISL9238 driver and ramping code. The
charger chip has been removed from the board since proto2.
BUG=b:65013352
BRANCH=none
TEST=Boot Fizz Proto3 on BJ and Type-C.
Change-Id: I32c2467f4ab23adf3f9313a03914d74d64a722df
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/668119
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Prepare the future and return a WebUSB descriptor to be able to use the
dongle from this website.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=twinkie
BUG=none
TEST=manual: enumerate WebUSB descriptors with lsusb and connect to
a WebUSB page in Chrome R61+.
Change-Id: I6a36538667ac114fc4b40cb87b2d6e946e265c4d
Reviewed-on: https://chromium-review.googlesource.com/677285
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Kionix Accel does not have FIFO, enable force mode for it.
Chrome needs sensor for screen orientation, set to to 10Hz
in S0 in the EC.
BRANCH=none
BUG=b:62029360
TEST=none
Change-Id: I5545580f2073e9d1145bd86cfcd594164119cae7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675575
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
The TCPC interrupts were setup, but they weren't enabled yet. This
commit enables the interrupts.
Additionally, a "tcpcdump" debug command is added. This can be removed
later or expanded upon to be more generic.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that we respond to TCPC alerts.
Change-Id: Iba9523cbfb96a570b76e7bdc0ba21dd782854f24
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670063
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes LED pulse using deferred call to save RAM and
CPU cycles.
This patch also adds led_alert API. It blinks LED as a warning.
BUG=b:37646390
BRANCH=none
TEST=Verify LED on in S0, pulse in S3, and off in S5.
Run 'led alert' command.
Change-Id: I8c61f91f095eed562d2ee9582868879241df626f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675749
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The WebUSB specification defines a specific Platform Descriptor in the
Binary Object Store:
https://wicg.github.io/webusb/#webusb-platform-capability-descriptor
This descriptor provides a special 'Landing page' URL to the host
browser and associated privileges for it.
Bump the USB version for BOS descriptors to 2.1 to be compatible with
Chrome implementation.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
BRANCH=twinkie
TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate
WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome
R61+.
Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6
Reviewed-on: https://chromium-review.googlesource.com/664813
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Just setting the global VRMODECTRL register is not enough to disable
the effect of SLP_S0# signal. Each VR control register needs to be set
correctly to ignore the effect as well. However, disabling VR decay on
SLP_S0# assertion by default results in additional power consumption
during S0ix. In order to prevent this, VR decay on SLP_S0# assertion
needs to be enabled and disabled dynamically as follows:
1. By default on EC boot, PMIC will be initialized to disable VR decay
on SLP_S0# assertion.
2. When host indicates intent to enter S0ix, EC will enable decay of
VRs on SLP_S0# assertion.
3. When host exits from S0ix and updates the intent to no longer enter
S0ix using host command, EC will disable decay of VRs on SLP_S0#
assertion.
actual SLP_S0# assertion because PMIC seems to honor the setting only
at SLP_S0# assertion and not if it is already asserted.
BUG=b:65732924
BRANCH=None
TEST=Verified with this change that the failing Lux device is stable
for a long time even with runtime S0ix.
Change-Id: I9c5afb408694b3b467e85dcea723f7574bc639c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/674034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change allows chipset and board to perform any action when host
indicates intention to enter sleep state. Chipset can take action like
enable/disable power signal interrupts and boards can enable/disable
decay of VRs on host intent to enter/exit S0ix.
BUG=b:65732924
BRANCH=None
TEST=make -j buildall
Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/677498
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to get a Twinkie firmware image with the regular Twinkie sniffer
firmware in the RO partition and a firmware behaving as a USB PD sink in
the RW partition, I had created the (questionable) build_rw_variant bash
script.
Now the EC build can do this natively, so remove the script and the
dedicated task list and use conditional task declaration in the
ec.tasklist.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=twinkie
BUG=none
TEST=build the former firmware with './board/twinkie/build_rw_variant',
build the new one with this patch and 'make BOARD=twinkie' -j,
compare the 2 resulting binaries, they are identical.
Change-Id: I3adb24e2c2825e5bd6f43a7440f829efd70038cc
Reviewed-on: https://chromium-review.googlesource.com/677284
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The dump_charge_state (chgstate console command) is quite large,
and may get truncated, let's add 2 cflush at approximately
each third of the output.
BRANCH=none
BUG=b:66575472
TEST=On wand, type chgstate in EC console
Change-Id: Iaa87a6a77b9b6edb0bd8235a87297f8d63fe3085
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/678755
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
update_dynamic/static_battery_info update information in the memmap
shared with the host. When there is not host, these functions
cannot do anything.
The battery information will, eventually, have to be passed to
host (through lid EC), but this will be implemented later.
BRANCH=none
BUG=b:66575472
TEST=make BOARD=wand -j
Change-Id: I1640bb0c5a9eb242183b957ccbef4d4999112160
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/678754
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT Rp is applied when neither port
is a source, so apply it at boot to be consistent.
BUG=chromium:766814
BRANCH=gru
TEST=On kevin, verify 3A Rp is applied to both ports at boot.
Change-Id: Ib62a96063783e8ef9ac9240800f445fa9e5a59af
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675845
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When battery is at critical charge level, reject charge port disable
request. Since battery is not able to provide enough power to the EC
on boot, we should not cut off our input power, regardless of
dual-role determination or other charging policy.
(Reference:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/351224)
BUG=b:64703097
BRANCH=None
TEST=make -j buildall. Verified that both right and left port are
able to boot the EC up successfully. No reboot loops observed in
critical battery conditions.
Change-Id: I098083036388783c0975ac772da3a3412895e26f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/675586
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Chromebox ECs performs EFS: verifying firmware before the AP boots.
This patch updates host commands which are required for the EFS.
When EC_REBOOT_FLAG_SWITCH_RW_SLOT is specified, EC_CMD_REBOOT_EC
changes the active slot before it reboots the system.
BUG=b:65264494
BRANCH=none
TEST=On Fizz, verify:
1. RW_B is old and updated by soft sync. RW_B is activated and
executed after reboot. System continues to boot to OS.
2. RW_A is old and updated by soft sync. RW_A is activated and
executed after reboot. System continues to boot to OS.
Change-Id: I08050c985ce0b27b30cb842e6b5b4660f32e5211
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648450
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When EFS finds the active slot is invalid, it tries the other slot.
This patch makes the other slot active so that the following boots
will try the other slot first.
This patch also replaces enum flash_rw_slot with system_image_copy_t.
The new APIs are therefore renamed from *_slot to *_copy. Basically,
this makes vboot see slots as a conceptual place instead of physical
spaces bound to flash storage.
BUG=b:65028930
BRANCH=none
TEST=On Fizz, verify:
1. RW_B is old and updated by soft sync. RW_B is activated and
executed after reboot. System continues to boot to OS.
2. RW_A is old and updated by soft sync. RW_A is activated and
executed after reboot. System continues to boot to OS.
Change-Id: Icf97da13e651e7a931b9d507052b9422566eb16c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648449
The Vbus adc channel was defined as 0 in the enum, however, we don't
actually have a Vbus ADC channel, therefore it should be defined as -1.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that when charge manager tries to read the
Vbus voltage, the EC doesn't panic due to a non-existing channel.
Change-Id: I53dd3259afc7ae76f587e5b7925ce2f9daa06402
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670123
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit enables the PSL pins for zoombini. Previously, we were
initializing the PSL_OUT pin to high, but it actually turns out that
setting the output from a 0 to a 1 indicates that the firmware wants to
remove Vcc1. This caused the EC to not boot up. This commit removes
the improper initialization of the GPIO and additionally sets up the
hibernate wake pins accordingly such that they can be used by the PSL
glue logic.
BUG=b:65647213
BRANCH=None
TEST=Flash zoombini without rework. Verify board comes up okay.
TEST=Enter `hibernate` on console; Verify board goes to sleep. Verify
that each hibernate wake pins wakes up the board successfully.
Change-Id: Ife1b82eec7957b44bbe409cdeba9c3972168812f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670062
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The keyboard config was the old chrome OS keyboard, but it should be the
new one introduced in April of this year.
Additionally, change KSO2 inverted to be push-pull instead of open
drain. This was causing the entire row to not be detected.
BUG=None
BRANCH=None
TEST=Flash zoombini; Verify that every key on the keyboard is detected.
Change-Id: I408739eed84f06bd9a2df5a9053c75859f8aaa0b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670061
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The LEDs were on when they were intended to be off. This commit just
inverts the duty cycles.
BUG=None
BRANCH=None
TEST=Flash zoombini. Verify all LEDs are off. Plug in battery, verify
that Red LED is on.
Change-Id: I78e2bce45603fd223ebaeacb024a210c5db70123
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/670060
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Was set in Hz unit instead of mHz.
The minimal frequency of the gyroscope is 25Hz.
By setting it at 25mHz, we make believe that the gyro was also
supporting 5Hz or 10Hz: the test would complain when instead the samples
came with a 25Hz.
Fix up of cl/482703
BUG=b:65000611
TEST=compile
BRANCH=caroline,eve,twinkie
Change-Id: I162d0d2e9b545af82698d8d484875761f426efe4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/674003
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Using builtin function in macro.
Compact macros.
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with LSM6DSM sensor connected
to I2C master interface of target board.
Using accelrate motion sense console command is possible to
test with different data rate: all supported ODR has been tested
for acc and gyro
Change-Id: Icb11f90254521715dfb2abb5bac6eb87ce45b92d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/465375
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This is used for factory test with following command
1. ectool command
ectool led power query
ectool led power green=100
ectool led power red=100
ectool led power amber=100
ectool led power off
ectool led power auto
2. console command
led debug >> enter debug mode
led green
led red
led amber
led off
led debug >> exit debug mode
BUG=b:65651340
BRANCH=master
TEST=`ectool ...` works good
Change-Id: Icb87e479075d90f509d60121a3e1df0afe66d41f
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/666418
This change makes the power LEDs pulse using PWM.
S0: solid green.
S3: pulsing amber (= mix of green and red)
S5: off
BUG=b:64975836
BRANCH=none
TEST=Verify LED behavior described above on Proto3
Change-Id: I696cf8279dd762236b7b7f000a316820d58916bf
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/669773
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This will be used by the updater to first check that the touchpad
FW on AP side matches the one for which we stored hashes on EC
side.
This guarantee that we do not accidentally try to flash an
incorrect FW, which would render the touchpad non-functional.
BRANCH=none
BUG=b:63993173
TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \
BOARD=hammer -j
TEST=./usb_updater2 -t
includes output of
sha256sum A459C-1211_ForGoogleHammer_3.0.bin
Change-Id: Id30ab2d7c7d7e2d0f25cc893f685d218c44c022e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/641736
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
After mulptiple edits of the script, there is a case when bash
variable is not properly quoted, let's fix it.
BRANCH=cr50
BUG=b:64698702
TEST=verified proper tag description set by git
Change-Id: I5847437cde717bb6e1f4b672fe6008b8e6e6f4e3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/667917
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
With longer git SHA1s reported by git commands and longer version
strings, the entire SHA1 could be not fitting into the 32 byte version
of the VERSION string. So, instead of adding the 'dirty' marker to the
end of SHA1 let's replace the prefix dash with it in case the tree is
dirty.
This way the length of the version string does not change (as long as
the 'dirty' marker is one character long).
BRANCH=cr50
BUG=b:64698702
TEST=verified output of running getversion.sh with a clean tree
$ ./util/getversion.sh | grep VERSION32
#define CROS_EC_VERSION32 "_v1.1.7046-591608e2e"
and a 'dirty' tree
$ ./util/getversion.sh | grep VERSION32
#define CROS_EC_VERSION32 "_v1.1.7046+591608e2e"
Change-Id: I42684522beaff9e9714206cfaddaf97e6cd644be
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665958
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In the USB 2.0 specification, the "8.5.3 Control Transfers"
chapter says that "When all of the data structure is returned to the host,
the function should indicate that the Data stage is ended by returning a
packet that is shorter than the MaxPacketSize for the pipe. If the data
structure is an exact multiple of wMaxPacketSize for the pipe, the function
will return a zero-length packet to indicate the end of the Data stage."
When doing a 'Control Read' transfer and the returned data (in IN
packets) was a multiple of MaxPacketSize, we were omitting the
zero-length packet and so the host was blocked waiting for a successful
IN transaction.
This corner-case was a regression introduced by the re-writing of the
control transfer handling done by CL 318864. So the STM32 USB code which
is similar to the former code is dealing properly with this case.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=cr50
BUG=none
TEST=manual, extend the configuration descriptor to be exactly 64 bytes,
and see the enumeration is no longer failing.
Change-Id: I108e8c6bb9eb727c41f3e1c607f0919fa1192d5a
Reviewed-on: https://chromium-review.googlesource.com/664814
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Make use of the generated touchpad firmware hashes to validate
the blocks before writing them to the touchpad.
BRANCH=none
BUG=b:63993173
TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \
BOARD=hammer -j
TEST=./usb_updater2 -p SA459C-1211_ForGoogleHammer_3.0.bin works
TEST=./usb_updater2 -p SA459C-1211_ForGoogleHammer_4.0.bin fails
Change-Id: If5d2be57b63e16ee81aa9acaf840c5084f9b92de
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/616371
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Based on the passed TOUCHPAD_FW parameter to the make command, the
build system generates hashes for the touchpad FW.
To generate the hashes, gen_touchpad_hash splits the touchpad FW
in blocks of CONFIG_UPDATE_PDU_SIZE, that are hashed individually
(SHA-256), and then stored in the EC image.
This will allow the USB updater code to verify the integrity of
the touchpad firmware being flashed.
When no FW is provided, zeros are output, which do not match
any valid data.
BRANCH=none
BUG=b:63993173
TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \
BOARD=hammer -j
TEST=Using variations of
make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \
BOARD=hammer -j
make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_4.0.bin \
BOARD=hammer -j
make BOARD=hammer -j
Check that TPHASH touchpad_fw_hash.h is only regenerated when
the parameter changes.
Change-Id: Ie347270aa9c00342de13489c9422e45e681b94c2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/615321
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some Elan touchpad ICs have a different firmware sizes (48, 56, or 64
KB). We use CONFIG_TOUCHPAD_VIRTUAL_SIZE, set in the board file, to
determine the appropriate size, and, at runtime, we sanity check the
firmware size according to the IC type reported by the touchpad.
BRANCH=none
BUG=b:65188846
TEST=Manually modify the CONFIG_TOUCHPAD_VIRTUAL_SIZE in hammer,
executed and verified both (1) "EC_ERROR_UNKNOWN" returned
(2) ic_type shows 0x09 on EC console
TEST=Successfully flashing 48k firmware using CL:658920 on hammer and
56k firmware on staff. With success here, we specifically test
with different firmware version and make sure it reflected in
hammerd's touchpad info.
Change-Id: Ib30917d8376d4a2e8b6137daabad2341ac48d1f8
Signed-off-by: Chun-Ta Lin <itspeter@google.com>
Reviewed-on: https://chromium-review.googlesource.com/664937
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Proto2 board has the line ADP_IN, which is raised to 2.5 V when a BJ
adapter is plugged. This patch makes EC running on proto2 and above
use this line to detect the power source at boot (as opposed to proto1
guessing a BJ adapter is plugged if PPVAR_BOOSTIN_SENSE is 19v).
BUG=b:37573548
BRANCH=none
TEST=Boot proto3 Fizz on BJ and Type-C.
Change-Id: I4052a73729d62694ce154bfb33255974dc110841
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/626879
The script tries to determine the upstream branch name, and finds out
which is the first sha1 of the current branch.
Then the script tags the branch and generates a git command strings
the operator is supposed to check for sanity and enter to push the new
tag to the server.
With the new tag set each following run of ./util/getversion.sh would
generate version strings including the new tag name and number of
patches above the branch point.
More implementation details are included in the comments in the
script.
BRANCH=cr50
BUG=b:64698702
TEST=tried the script in cr50 and gru firmware branches:
cr50$ <path to>/tagbranch.sh
A new tag 'v1.9308_B.0' has been set. Use the following command
to push it to the server
git push --tags https://chromium.googlesource.com/chromiumos/platform/ec v1.9308_B.0
Or if you want to delete it:
git tag -d v1.9308_B.0
cr50$ ./util/getversion.sh | grep -w VERSION
#define VERSION "_v1.9308_B.192-b5c9d0aa7"
cr50$
cr50$ cd <path/to>gru
gru$ <path to>/tagbranch.sh
A new tag 'v1.8785_B.0' has been set. Use the following command
to push it to the server
git push --tags https://chromium.googlesource.com/chromiumos/platform/ec v1.8785_B.0
Or if you want to delete it:
git tag -d v1.8785_B.0
es^o: ~/new_projects/gru-8785/src/platform/ec 175 > ./util/getversion.sh | grep -w VERSION
gru$ #define VERSION "_v1.8785_B.218-5d857ed8c"
gru$
Change-Id: I0c0067f6b7bb837a0c119bc14ff48cb9223a3fa5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656575
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Servo / Suzy-Q related debugging methods is a big challenge
in factory especially after servo debug header is removed.
Expose some information to OS from EC will do a great help
for massive production.
+ expose charge/battery related state to ectool
1. chg_ctl_mode
2. manual_mode
3. battery_seems_to_be_dead
4. battery_seems_to_be_disconnected
5. battery_was_removed
6. disch_on_ac (learn mode state)
7. battery DFET
BUG=b:65265543
BRANCH=master
TEST=`ectool chargestate param x10000~0x20006 get correct state`
Change-Id: Ib64ab3c7b68a634ea098425c93e5234361cd1936
Reviewed-on: https://chromium-review.googlesource.com/662318
Commit-Ready: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Tested-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
