eCTS tests are small. We can use smaller flash size to expedite
tests. This patch reduces flashing time for stm32l476 from 24 sec
to 6 sec.
BUG=chromium:736020
BRANCH=none
TEST=python util/run_ects.py
Change-Id: I829ee2c947664f2d7ed373f52ff336e9a9580817
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/553580
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In a different environment, returned characters are corrupted if
baudrate isn't specified. This patch replaces tty_read method with
the one using pySerial.
BUG=chromium:736778
BRANCH=none
TEST=Run run_ects.py and verify all tests pass.
Change-Id: I8c14f6a04c900d2670ad86c1b91f3fe6625ba69c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/550848
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch adds i2c suite to run_ects.py. It also adds checks for
return values from i2c_read and i2c_write functions.
BUG=chromium:653183
BRANCH=none
TEST=Run run_ects.py and verify all test pass.
Change-Id: Ie3d6e1e6f131235e2b28f39e1546c9cb4c3b92f6
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/547024
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since the script is expected to upload results and probably send
alerts by e-mail, it's better to be written in Python so that we
can utilize chromite library. It will no longer run outside chroot
because of imports from chromite.lib.
BUG=chromium:735546
BRANCH=none
TEST=Run run_ects.py and verify all tests pass.
Change-Id: I6c79b061cdaef4d30305cf531f37b6734d18b7d9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/546579
Reviewed-by: Randall Spangler <rspangler@chromium.org>
looks like we had a bit of a race condition: set_state() was
effectively just an assignment opration to pd[port].task_state. it's
called asynchronously from pd_set_suspend() in response to a
PD_SUSPEND message from the AP as well as from pd_task() before it
enters its main event loop. this can take a long time because
tcpci_tcpm_init() has a 300ms timeout. last one wins.
similarly, when pd_task() is running its main loop, pd_set_suspend()
really needs to wait for pd_task() to actually enter the
PD_STATE_SUSPENDED state before the caller can assume that the
pd_task() has stopped accessing the TCPC.
the particular failure case was when depthcharge would decide to do a
TCPC firmware update. it starts by sending a PD_SUSPEND to the EC,
then accessing the TCPC. unfortunately, the pd_task() hadn't gotten
out of the way yet, thus causing TCPC access chaos.
so, i'm adding a req_suspend_state flag to the pd_protocol struct so
we can tell pd_task() to suspend itself in a controlled manner. when
pd_task() is ready to do a state change - basically at the top of the
main event loop - it'll change to PD_STATE_SUSPENDED and clear the
req_suspend_state flag.
in any case, pd_set_suspend() still needs to wait around for pd_task()
to enter the suspended state as we don't have a fancy handshake
mechanism between these tasks.
TEST=in combination with some follow-on CLs, ps8751 firmware update
works properly where previously it needed a ~2 second delay
for the EC pd_task() to settle. the way to trigger the
failure was to insert or remove the power brick.
BRANCH=none
BUG=b:62356808
Change-Id: I363803ff60db31ccf84d592f8c9d1610fbe0f9ce
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/544659
Reviewed-by: Shawn N <shawnn@chromium.org>
Recovery mode can be triggered with or without hw reinit. And both the
modes are triggered using the same button combination held down for
different amount of time. For recovery mode with hw reinit (>30
seconds), LED blinks for 4 seconds. However, for recovery mode without
hw reinit(>10 seconds), there is no user indication. This change turns
on the LED as soon as the >10 second condition is satisfied. This
provides an indication to the user that recovery mode is triggered.
BUG=b:62886608
BRANCH=None
TEST=make -j buildall
Change-Id: I949c3e7e98441131df987b6351c1f614f3b4831c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/549775
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
flash_physical_protect_now(), which is called when
EC_FLASH_PROTECT_ALL_NOW is set, should protect the entire flash
temporarily until reboot. Current behavior enable flash protect on all
region permanently. The correct implementation should be writing an
invalid key to the flash controller to disable flash flash only
temporarily until reboot.
Since the implementation of flash-stm32f3 and flash-stm32f4 is almost
the same after restoring the changes made in commit
35f4d8acaa, we merge to file by creating a
symlink from flash-stm32f3.c to flash-stm32f4.c to reduce code
duplication.
BRANCH=none
BUG=b:37584134
TEST=on eve:
1) `ectool --name=cros_tp flashprotect`
Flash protect flags: 0x00000008 wp_gpio_asserted
2) `flashrom -p ec:type=tp --wp-enable
3) `ectool --name=cros_tp reboot_ec`
3) `flashrom -p ec:type=tp --wp-status`
WP: status: 0x80
WP: status.srp0: 1
WP: write protect is enabled.
WP: write protect range: start=0x00000000, len=0x00040000
4) `ectool --name=cros_tp flashprotect`, all_now should present
Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now \
all_now
5) `ectool --name=cros_tp reboot_ec; sleep 0.3; \
ectool --name=cros_tp rwsigaction abort` to stay in RO.
In EC console, `flashinfo`, should show that only RO is actually
flash protected:
Protected now:
YYYYYY..
6) `flashrom -p ec:type=tp -w ec.bin -i EC_RW` works
7) `make BOARD=ryu -j` works (for testing flash-stm32f3.c)
Change-Id: Ia7a60ae8b3084198abb468e4fc8074b4445d6915
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/549681
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
If we have requested the host to go to recovery mode, the host will
usually not need an RW hash because it won't do EC SW sync. Therefore,
do not auto-start calculation of our hash if we've requested recovery.
This may avoid past recovery-breaking bugs due to unexpected RW contents.
If the host does need the hash after all, it will manually request that
the computation start.
BUG=chromium:612966
BRANCH=None
TEST=Boot to recovery mode on kevin, verify that "hash start" print is
not seen on UART.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I66d2d74398357dfe30e39882feec8cfba4cc945c
Reviewed-on: https://chromium-review.googlesource.com/540695
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a delay before flash_erase deferred started so the task does not halt
CPU, and cause the response of EC_CMD_FLASH_ERASE to not be delivered.
When the above situation happens the host I2C controller will timeout.
A 100ms delay should be long enough on any board to allow the response
to be sent.
BRANCH=none
BUG=b:38018926
TEST=on eve units where flashrom always fail:
`flashrom -p ec:type=tp -w ec.bin` succeeds.
Change-Id: I399a60064392da41a3e27f8630175ab427047ab7
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/547375
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
This patch updates the mutex test suite so that it can be run
within the current framework.
BUG=chromium:736155
BRANCH=none
TEST=run cts.py -m mutex
test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT
lock_unlock_test SUCCESS SUCCESS 1 1 PASS
Change-Id: I69ee0857a0c633d7c6c8909f8c6f58ca6fd272ce
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/544790
This patch makes each test print start marker before sync. This will
allow us to distinguish the failure before even sync is attempted
(CTS_RC_DID_NOT_START, thus probably caused by the previous test)
and the failure caused by the hanging partner, in which case the one
good and alive will be stuck in sync (and should return _DID_NOT_END
or even better _BAD_SYNC once we implement timeout in sync).
This patch also:
* Adds did_not_start_test to and removes debug_test from meta suite
* Consolidates test runner loops into common cts_main_loop
* Removes dut_common.h and th_common.h
* Removes debug print macro and CTS_DEBUG
* Replaces all infinite loops after tests with task_wait_event(-1)
* Removes meaningless comments and debug printfs
* Removes CTS_TEST_ID_*
* Adds sync() to task suite
BUG=chromium:736104
BRANCH=none
TEST=Run run_ects.sh and verify all tests pass
Change-Id: I6ccdf26afac6b8e8cb16483c5d75e4e77e7962f4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/545176
This patch updates the hook test suite so that it can be run
within the current framework.
BUG=chromium:736047
BRANCH=none
TEST=cts.py -m hook
test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT
test_init_hook SUCCESS SUCCESS 1 1 PASS
test_ticks SUCCESS SUCCESS 1 1 PASS
test_priority SUCCESS SUCCESS 1 1 PASS
test_deferred SUCCESS SUCCESS 1 1 PASS
Change-Id: I3e7f29da61e794b06b03241f3d7706c2db94b5be
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/545084
The Eve board defines left and right LEDs, but the LED control loop is
checking for auto control to be disabled on the power/battery LED IDs.
This is breaking factory testing for LED colors when the battery level
is low because it is flashing RED and ignoring the colors that the
factory software attempts to set.
BUG=b:63049012
BRANCH=eve
TEST=manual testing on Eve with low battery
Change-Id: I65b822111b3054a5994d71ec4e2a089c487acf97
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/549740
Reviewed-by: Todd Broch <tbroch@chromium.org>
the EC firmware build for chell ran out of space, so i'm turning off
some CLI commands. i'm turning off all the commands we've already
turned off for kevin (see board/kevin/board.h).
TEST="make buildall -j" passes
BUG=b:62356808
BRANCH=none
Change-Id: Ie7191f841d826cefc8b17f5325b221842db2eb1d
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/544095
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Don't discard irqprio data when the IRQ_PRIORITY macro is used directly
(for watchdog / watchdog timer).
This change is probably a NOP for all platforms, since the power-on
default for the IRQ prio register seems to be zero, which is the same
priority we're setting in our direct use of IRQ_PRIORITY.
BUG=chromium:634701
BRANCH=None
TEST=Verify 'prio_44' entry exists in irqprio section by checking
ec.RO.map on kevin.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idaffc484a2ce4749c18212f179b3951ff570aed0
Reviewed-on: https://chromium-review.googlesource.com/545201
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On a keyboard-less, volume-button-less board, we support simplified
sysrq handling.
For Fizz, we use the recovery button to trigger sysrq event and
holding it down to trigger warm reset.
BUG=b:38418116,b:38417391
BRANCH=none
TEST=On Fizz, try
1. Press recovery button and release -> sysrq sent
2. Press and hold recovery button -> warm reset
3. Press recovery button and power button -> enter recovery mode
Change-Id: If8760319dba3df4545e9805b396ac89c241dae80
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/537817
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This script will run nightly in the lab and publish the results.
Publishing results will be implemented later.
BUG=chromium:735546
BRANCH=none
TEST=Run run_ects.sh inside & outside chroot and verify all tests pass.
Change-Id: I405ea601eff33f1a4328f2606c8bb4050ff8d253
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/543681
We need to add a few library routines for sensor task.
Routines added are taken from nds32's library.
BRANCH=none
BUG=none
TEST=Add sensor task to reef_it8320 board.
Test screen rotation functionality on reef_it8320.
Change-Id: I2eee33f897b38e05bddd30b16f875944259b2c0d
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/527537
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If we don't strip a serial string read from a file, TH serial doesn't
match with the one read from lsusb. It causes TH to be recognized as
a DUT.
This patch also makes error messages more helpful when DUT is not found
or multiple DUTs are connected.
BUG=none
BRANCH=none
TEST=cts/cts.py -m meta, task
Change-Id: Ifcf96089b9620ef8809a7d2924dacf67d3af419c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/542019
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Openocd is upgraded to 0.10.0, which supports stm32l476. So, now
we can run eCTS inside chroot. This allows new developers to spend
no time on setting up software as all necessary tools (e.g. specific
version of make, openocd, lsusb, ARM toolchains) come with cros_sdk.
BUG=chromium:653949
BRANCH=none
TEST=cts/cts.py -m meta
Change-Id: Iba7ba94e95ceadcedcb53b76e47054ba1b2b47dd
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/542017
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch makes the framework verify not only the result but also
the execution order of the tests. It also allows each test to
specify expected return code and strings printed by TH and DUT.
The final test results depends on the return code and the expectation.
Therefore, the output now includes 'RESULT' column showing PASS or FAIL:
test name TH_RETURN_CODE DUT_RETURN_CODE TH_STR DUT_STR RESULT
test_task_switch SUCCESS SUCCESS 1 1 PASS
test_task_priority SUCCESS FAILURE 1 1 FAIL
test_stack_overflow DID_NOT_END DID_NOT_END 1 1 PASS
Additionally, this patch:
* Adds CTS_RC_DID_NOT_START and CTS_RC_DID_NOT_END to indicate whether
the test did start or end, respectively.
* Makes stack overflow test check whether stack overflow was detected
and reboot occurred
* Removes post_corruption_test and conflict test since now
the test results are stricly compared against expected results.
* Fixes gpylint errors.
BUG=none
BRANCH=none
TEST=Run gpio, meta, timer, interrupt, and cts/cts.py -m task
Change-Id: I3b7005236e705dcac0c8f4711b44c85ff9a4f676
Reviewed-on: https://chromium-review.googlesource.com/538878
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This patch adds a test for stack overflow detection. CTS task tries
to overflow by calling a function recursively. This function sleeps
to incur context switch, where stack overflow is checked. Reboot is
expected but not checked.
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: I6ad98d209acf873d2d23b48bac6fc751fa8c2f74
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410283
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We need to refactor power/rk3399.c to make it more flexible
to support different power sequences for upcoming follower boards.
BUG=b:62640322
BRANCH=none
TEST=manaully test on scarlet and kevin:
S0->S3->S0 and S0->S3->S5->G3->S5->S3->S0 work.
Change-Id: I70cdcbaba046bfab4fe832eca58f30524e99e6de
Reviewed-on: https://chromium-review.googlesource.com/540783
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Implement the necessary bits for updating the trackpad firmware over
I2C, primarily following the protocol from open source driver.
BRANCH=none
BUG=b:35587174
TEST=Manually update firmware and confirmed reported FW version changed.
Change-Id: Ice5098269803f524de0b6a853f5a98f28382a7fb
Reviewed-on: https://chromium-review.googlesource.com/532765
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The INFO1 mask field contents serves as input for the rollback
protection mechanism, when the RO decides if an RW is allowed to run
on the device.
The existing code updates INFO1 mask to match the lowest rollback
priority of the two images (RW_A and RW_B) present on the device.
INFO1 mask should be also updated when the current image is endorsed
by the host. In this case the alternative RW is destroyed, so the
INFO1 mask could be set based solely on the currently running image.
This patch refactors the code to allow setting INFO1 mask based on one
or both RW headers' contents.
BRANCH=cr50
BUG=b:62138152
TEST=verified that "normal" INFO1 mask updates still work as before,
the mask is modified to match the image with the lowest rollback
priority.
Also verified that when the VENDOR_CC_INVALIDATE_INACTIVE_RW
command is received the INFO1 mask is updated based on the
currently running image.
Change-Id: I23172388674e1f3a4c2489e139dd197a84029f54
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/541738
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This change will configure camera PMIC to low power mode
in S3 and S0ix sleep state and resumes it in S0 state.
BUG=b:62779726
BRANCH=None
TEST=`Build/Flash EC and verify the PP3300_DX_CAM signal is
toggling during S3/S0ix cycle.`
Change-Id: I9f376762100ac9b208df4a39160e4acd3b7b925e
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539316
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not
CONFIG_R*_MEM_OFF. The previous implementation happened to work for
internal mapped storage (eg. stm32) but failed for external mapped
storage which is copied to SRAM before execution (eg. npcx).
BUG=b:62841029
TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump
and sig verification continues to work on fizz and stm32.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7
Reviewed-on: https://chromium-review.googlesource.com/541861
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be
clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks
can be in the right range. When APBX prescaler != 1, it results in 2x
timer clocks on both APB1 and APB2. We added a new
clock_get_timer_freq() function for stm32 to get timer specific clock
frequency so we can return 2x timer clocks when APBX != 1.
Flash latencies also need to be changed when we clock at 96MHz, the
FLASH_ACR_LATENCY defines are moved into the variant-specific switches
so each board can defined latency when setting CPU clocks.
BUG=b:38077127
TEST=`make BOARD=rose -j`, touch performance improved by 2x.
Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444
Reviewed-on: https://chromium-review.googlesource.com/539375
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
the 1ms reset hold time isn't in the ps8751 datasheets (yet), but
that's what our parade support contact recommended. i'm applying this
fix to reef (electro) and coral as these two boards were missing any
sort of reset hold time. other boards using the ps8751 seem to
already have a 1ms or 10ms delay.
TEST=rebuilt, reload EC image on electro... no ill effects noted.
BUG=b:62642003
BRANCH=reef
Change-Id: I39a989375e789118d062f82e9baaa041e5e6b033
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/540742
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Recent changes broke the portability of this header file.
Fix the ACPI guards so it can be used in coreboot.
BUG=b:36024430
BRANCH=none
TEST=make -j buildall (as usual many haven boards fail)
Change-Id: I0d737e7aad7ead90289b43db09352092ef7e3e98
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/539135
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This API checks battery charge level and current power supply
to determine whether the AP has enough power to boot or not.
BUG=b:38462249
BRANCH=none
TEST=make buildall
Change-Id: I489f7ea92f230701b8f18c94d3e698aad90b4a03
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/517272
This patch adds wait between DSW_PWROK and PWRBTN assert. It is
required to be 95 msec or longer for Kaby Lake and Sky Lake.
Refer to the timing diagram for G3 to S0 on Sky Lake or Kaby Lake
platform design guide for details.
BUG=b:62584658
BRANCH=none
TEST=On Fizz, measured time between DSW_PWROK high and PWRBTN assert
for 1:AC plug-in, 2:recovery+power press, 3: reboot ec command.
Change-Id: I89a14ac9a49e20a332bd662d90be62f8ea23b003
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/534901
Reject updates for the first 60 seconds after a hard reboot. This should
prevent people from using the reboot at the end of an update to get
around the update rate limiting. Reboots don't happen during normal cr50
operation, so this should not prevent updates. It will just prevent
updating cr50 many times in a row.
This change does not limit updates after deep sleep or POR.
BUG=b:62097097
BRANCH=cr50
TEST=Try to update cr50 two times. Verify that on the second time the
update is rejected. Put cr50 into deep sleep, wake it up and verify it
can be updated immediately. Get cr50 to do a POR and verify it can be
updated immediately.
Change-Id: I828ef210e1c5bcf59d4753b8178ee4e1369d5d36
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/520727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Until HOOK_INIT has completed, do not allow any tasks other than HOOKS
or IDLE to be scheduled. Programmers often make the assumption that
a HOOK_INIT function is guaranteed to be run before task code that depends
on it, so let's make it so.
BUG=chromium:649398
BRANCH=None
TEST=Manual on kevin, compare boot without patch:
...
[0.004 power state 0 = G3, in 0x0008] <-- from chipset task
RTC: 0x00000000 (0.00 s)
[0.004 power state 4 = G3->S5, in 0x0008]
RTC: 0x00000000 (0.00 s)
[0.005 clear MKBP fifo]
[0.006 clear MKBP fifo]
[0.006 KB init state: ... <-- from keyscan task
[0.012 SW 0x05]
[0.155 hash start 0x00020000 0x00019a38]
[0.158 HOOK_INIT DONE!]
... to boot with patch:
...
RTC: 0x58cc614c (1489789260.00 s)
[0.004 clear MKBP fifo]
[0.005 clear MKBP fifo]
[0.010 SW 0x05]
[0.155 hash start 0x00020000 0x000198e0]
[0.157 HOOK_INIT DONE!]
...
Also, verify kevin boots to OS and is generally functional through
sysjump and basic tasks, and verify elm (stm32f0 / cortex-m0) boots.
Change-Id: If56fab05ce9b9650feb93c5cfc2d084aa281e622
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/456628
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Cortex-M4 supports a floating point square root function that takes 14
cycles to execute, which is a speed improvement over the existing binary
search, and saves flash space.
BUG=chromium:687624
BRANCH=None
TEST=On kevin, verify that both sqrtf methods (binary search vs HW
instruction) have identical results for fractional input (eg.
sqrt(15.999999) = 3), except when floating point representation of
square root rounds up to an integer. Verify identical results for all
integers [-100, 16793602). Note that 16793602 is the first integer for
which the floating point representation of sqrt rounds up to an integer.
Also verify basic motion sense functions on kevin.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I8521c9a28c958b340ca83c37342253e424df0c91
Reviewed-on: https://chromium-review.googlesource.com/537734
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If Cr50 happens to start on a chip where Board ID programmed in INFO1
does not match the contents of the RW header, it means that for some
reason the other RW is not operational and the current image is the
only viable one.
In this case the Cr50 starts but operates in limited mode (only
commands for updating the image and reporting state are handled). In
this case the reason for recovery could be seen on the Recovery
screen, and the update could be done once Chrome OS boots in recovery
mode.
BRANCH=none
BUG=b:35586335
TEST=verified the following:
- if an image with wrong board ID is started, it tries to fall back
(sets the counter to a value above threshold and reboots)
- if the fallback fails, the image keeps running in the limited
capabilities mode but the update is possible, observed that the
new image took over worked after powercycling the device.
- observed proper error message on the recovery screen showing where
the error comes from
Change-Id: I46ba75392f8e891bb8503fb15aea2c56b5805e83
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/535978
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, read_tty reads characters from tty as long as there
is something to read. This causes read_tty to loop forever if the board
is in reboot loop.
This patch makes cts.py stop reading tty if boot count exceeds
max_boot_count. Reboot is detected by detecting REBOOT_MARKER.
This patch also does:
- Remove debug option: This adds complexity for no real value. Developers
should debug tests using regular tools (make, uart console, etc.).
- Remove html output. Nobody use it. Should be redone when it's needed
using proper libraries.
BUG=chromium:664309
BRANCH=none
TEST=cts.py -m task/gpio/interrupt
Change-Id: I51d1dd51c4097e8115ef04ad46853720295141b4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410281
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch hides expected messages from output to the terminal
and reorganizes log directory as follows:
- All test output goes under /tmp/ects/$dut/$module
- Openocd output is recorded in openocd.log
- uart outputs are recorded in uart_th.log and uart_dut.log
- build output is recorded in build.log
- Check exit code from all subprocess calls
- Dump build log if build fails
- Dump openocd log if openocd fails
BUG=chromium:664309
BRANCH=none
TEST=cts.py --setup and build images in chroot then run cts.py -m meta
outside chroot.
Change-Id: I13294c3bf777ad7ae590459d3cf5aea405d59f96
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409536
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add support for update related vendor commands in mn50 by relocating
relevant code from board/cr50 to chip/g.
BUG=b:36910757
BRANCH=None
TEST=./extra/usb_updater/usb_updater -d 18d1:502a build/mn50/ec.bin
Change-Id: Iec0fe5585b5b6eb099f9254dfb0e5b02d5106abc
Reviewed-on: https://chromium-review.googlesource.com/537999
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
