Replace ADC-based board version with CBI/EEPROM board version. This will
cause all of the existing boards to report -1 (or 65535) as their
board version until you can update it from the kernel.
To set your board version to 0 run the following command in
the AP console when WP if off (e.g. battery removed)
$ ectool cbi set 0 0 1 2
BRANCH=none
BUG=b:77551185,b:77900842
TEST=wrote to cbi from ap console and verify flash state on
ap and ec console
Change-Id: I03987cc89ca4c14580dcf61de23780fe5304663b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1008832
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently we only support the Acer LG and Panasonic battery. There is
a 3rd Acer battery type that Quanta could be providing us with for
Yorp proto boards. This CL adds support for the Sanyo battery.
BUG=b:74132235
BRANCH=none
TEST=verifed that when connected to Sanyo battery that the battery is
reported as present.
Change-Id: I1810da59866795e93340163216412441be098795
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1011557
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This CL adds support to check if the OCM flash is erased and if not,
will erase it at initialization time. These changes are encapsulated
in a new config option CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE and this
option is enabled for Yorp boards.
BUG=b:77658388
BRANCH=NONE
TEST=make -j buildall. Tested on a board that hadn't yet been
erased. Verifed the message
"anx7447: OCM flash checked and successfully erased"
was in the EC log, but did not show up on subsequent reboots.
Change-Id: I660e76a9498d3dc1ba821a04317b324f716c5089
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/988414
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
this adds control over the USB high speed muxes as a function of DP
HPD. this allows an external monitor to be added/removed with
chromeos extending the display as appropriate.
BUG=b:77151172
BRANCH=none
TEST=chromeos detects external monitor plugin and extends display
Change-Id: I7df7a8136ddaa4eeaca800d29b46350dafd8f838
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1009208
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Since there are known issues with ANX7447 driver to work
reliably in low power mode, disable DRP_AUTO_TOGGLE option
since TCPC_LOW_POWER mode config and this one should be disabled
together.
BUG=b:77544959
BRANCH=None
TEST=On yorp; on port 0 and 1 test without and with battery boots up.
Please note with battery we may still need to press power button to
get the SoC to boot up to S0 b:76230069.
Detaching the Type-C charger with battery connected also shuts down
the system which is a known failure b:77606986.
Change-Id: I1b744cd9aa063328845f9a1cc7e36d291dfec9f5
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1007629
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Instead of doing I2C traffic in an init hook, move it to a
deferred function to be called outside of INIT_HOOK processing.
(identical to CL:1001474 on eve branch, moved to poppy board
file)
BUG=b:77336348
BRANCH=poppy
TEST=while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done for 24 hours
Change-Id: Icd9c2096ca026da6308b74582144886b30ea965f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1003436
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The Cheza EC requires EC_RX_H1_TX be held low while the EC is being
reset to enter gang mode. This change adds another programming mode to
ec usb spi programming to do that.
BUG=b:74388083
BRANCH=cr50
TEST=The cheza boards aren't in, so I just tested EC_TX_CR50_RX_OUT
gpioset EC_TX_OUT 0 and 1 setup EC_TX_CR50_RX_OUT correctly as an
output when asserted and an input when deasserted.
Change-Id: I7fc9cba954f2af5a841f00ce5bf8a27251b33bbe
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1003529
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
charge_prevent_power_on() had sections which were gated on the following
CONFIG_* option:
CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT
However, the block of code that this gated didn't even take the battery
percentage into account and made it very confusing as to why.
This commit simply changes the CONFIG_* option used to gate to be the
following:
CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON
This better reflects the checks that were actually being made.
Additionally, this CONFIG_* option is defined by default for boards that
have a chipset task and is initialized to 15W, which is the power that
indicates that the charger is likely to speak USB PD.
BUG=b:76174140
BRANCH=None
TEST=make -j buildall
Change-Id: Ic9158dd7109ce6082c6d00157ff266842363b295
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/977431
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
This code enables alternate mode path for
DP for both TypeC ports.
BUG=b:77496487
BRANCH=None
TEST=On yorp; check if the mux is set correctly
for DP use cases. When PD message for hot plug is received
by EC, EC (write register) ---> TCPC (GPIO) ---> SoC,
and display comes up with both ports.
Change-Id: Idfd0f85dc02a04adb266f2755a6d68dcb20141f8
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1003330
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
It appears that the shared memory buffer on Nautilus starts at
200c7720 D __shared_mem_buf
That's 29.78 kb into the RAM. Software sync needs 1kb, so we should
be fine, expect that the last 2kb of RAM are supposed to be reserved
for the "booter" (NPCX_BTRAM_SIZE).
We shrink the accelerometer FIFO to 512 entries, freeing up 4kb of
RAM, and increase the UART TX buffer to 4kb, to make use of 3kb of
that freed up space:
200c7320 D __shared_mem_buf
That's 28.78 kb into the RAM.
BRANCH=poppy
BUG=chromium:739771
TEST=make BOARD=nautilus -j, check that shared_mem_buf offset is
< 29 kb.
Change-Id: I361a439b847d31d3415f2ee66229bd32f8816e2d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1002712
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When using VBUS_DETECT_TCPC the charger code relied on the TCPC
alert to initialize the VBUS supply, but that happens too late in
board startup sequence to allow an initally plugged in USB-C power
supply to be chosen as the active charging port.
We can and should initialize the the supplier sooner as to prevent
the charge_manager_is_seeded() check from failing thus preventing
the board from choosing a charging port.
BRANCH=none
BUG=b:77458917
TEST=PS8751 on yorp will negotiate 20V over USB-C (which was prevent
by the charge_manager not being seeded)
Change-Id: I6f612c508932a90ece0036ce8310a20de02d8467
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/994707
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With 3 binary strapping pins, we only have 7 available board ids:
000, 001, 010, 011, 100, 101, 110, 111.
Let's make the MSB of board id tristate. So we can have 4 more
board ids to use:
Z00, Z01, Z10, Z11.
BUG=b:77731277
BRANCH=poppy
TEST=build nautilus
Change-Id: I7aebb89437d2ccb9eea6c477155b25d964983232
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1000875
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Increase the size from 1024 to 4096 to reduce the likelihood of
overflows. To make space for the larger buffer, we reduce
CONFIG_ACCEL_FIFO to 512 entries (from 1024 entries: saves 4096
bytes of RAM).
grep shared_mem_buf build/lux/RW/ec.RW.smap
Before this patch:
200c74e0 D __shared_mem_buf
After this patch:
200c70e0 D __shared_mem_buf
(we saved 1024 bytes of RAM)
BRANCH=poppy
BUG=b:77159941
TEST=Flash lux, see that we do not lose EC logs in /var/log/cros_ec.log.
Change-Id: I320c370369364b280e59f490a86f057fbb502da3
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/983080
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This is based on the initial code from Caveh here:
https://chromium-review.googlesource.com/959861
Most things are functional, with some workarounds for P0 boards.
The type-c hotplug is not working in this commit, the HPD will be
run from the tcpm in the next board build. For now we might be
able to get it working on P0 with some more tweaking..
The other known issue is that the battery takes ~2 seconds to
come back online after a cutoff (the auto-power-on timeout is
one second so the board will not power on like it should) and
sometimes the battery is not responding properly on i2c and it
requires an EC reset.
BUG=b:75070158
BRANCH=none
TEST=tested on P0 boards
Change-Id: I438cb93b78d6f501426842d6cbe3d6a994563358
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/982498
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Port 0 uses the Anx7447. This CL updates the tcpc config to use the
Anx7447 driver instead of the Anx74xx driver.
BUG=b:74127309
BRANCH=NONE
TEST=make -j BOARD=yorp and verified that when connected external type
C charger to port 0 it reaches SNK_READY
Change-Id: I96967a1d272fcda079280ba6d2f0eb5ed8e3dd7f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982894
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Enable Gyro and collect data with FIFO.
BUG=b:73546254
BRANCH=master
TEST=Check gyro data is correct when enabled.
Run CTS test: cheets_CTS_N.7.1_r15.x86.CtsHardwareTestCases
Change-Id: I41321cfc8e7b4f8a006ee45c3a9d11305761315d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/986918
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Use RMA public key definition generated based on the binary blob
containing the key and key ID.
Key generation is controlled by the make file in common/, but actual
key blob comes from the board directory.
The structure holding the key and key ID is being modified to allow
initialization using a flat array.
No more need in defining CONFIG_RMA_AUTH_SERVER_PUBLIC_KEY and
CONFIG_RMA_AUTH_SERVER_KEY_ID.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST='make buildall' still succeeds.
test RMA server generated authentication codes are accepted when
unlocking RMA.
Change-Id: I8ade94de6eb69b3e49bc5b948dbac20e59962acf
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Driver implements TCPC for ANX7447 chip. Enable Type C
port for USB and DP alt mode.
BUG=b:73793947
BRANCH=NONE
TEST=tested compiled binary for pdeval-stm32f072 board with this patch.
Power contract establishment, port role swap, DP alt mode works fine.
Change-Id: Ic11e499fc5fb4aba7732c75e4cb2fee54828c616
Reviewed-on: https://chromium-review.googlesource.com/956790
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Majority of the chipsets do not have a dedicated GPIO to trigger
AP cold reset. Current code either ignores cold reset or does a warm
reset instead or have a work around to put AP in S5 and then bring
back to S0. In order to avoid the confusion, removed the cold reset
logic and only apreset is used hence forth.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Manually tested on GLKRVP, apreset EC command can reset AP.
Change-Id: Ie32d34f2f327ff1b61b32a4d874250dce024cf35
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/991052
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This patch brings in both prod and test RMA server public keys as two
binary files.
A bash script for converting binary blob into C definition is also
provided.
BRANCH=cr50, cr50-mp
BUG=b:73296144, b:74100307
TEST=none yet
Change-Id: I2edd78164b8c912408ac7eda2e0a3a0262a8e81f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/990782
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable trackpad power when chipset is in S0 state. Keep
it disabled in other states.
BUG=b:73137125
BRANCH=master
TEST=On Octopus, kernel logs show ELAN enumerated
Change-Id: Ie1fd8ab777e82d900418127b4efee29fe65d1423
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/984405
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
If we enable charge termination when booting w/o battery,
charge termination would trigger and cut the power for max17055.
BUG=b:72697658
BRANCH=scarlet
TEST=Read rt946x reg 0x02, confirm charge termination is
disabled when booting w/o battery, and enabled otherwise.
Change-Id: I5780196ad993299ddfb37621bee5e941aa9b0d14
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/989314
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
This CL adds required code to the tcpc_alert_event() and
tcpc_get_alert_status() functions. In addition, it adds
board_tcpc_init().
The ANX7447 does not have an EC controlled reset line. Other than that
modification the actions taken in tcpc_alert_event and
tcpc_get_alert_status are the same as what's been done of previous
projects using these TCPCs.
board_reset_pd_mcu still needs to be implemented, but is not related
to the tcpc_alert_event() and tcpc_get_alert_status() functions. Also,
at this point ANX7447 is not supported as that depends on the driver
landing.
BUG=b:74127309
BRANCH=none
TEST=Verifed that with external charger that USB PD state machine
advances to SNK_READY state. Note that port 0 does not work at all in
this version.
Change-Id: Ib887b4dba6bacb4b3fb6e03f634362e1c3aa4da2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982518
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
system_rollback_detected is used to determine if the system rolledback
in the rest of the system code base and it's state is saved longer. This
change switches board.c to use that to determine the sysinfo output
instead of using the reset count.
The reset count is cleared when the system boots. Depending on how fast
the system boots it may be difficult to read sysinfo before the reset
counter is cleared. In these cases it is difficult to tell whether an
image has been rejected entirely or the image caused a rollback.
BUG=b:71804463
BRANCH=cr50
TEST=boot the device. Make sure sysinfo shows there's no rollback.
Rollback and make sure sysinfo shows the system has rolledback
Change-Id: Ic29b105c758d0984e47482b9384cf00fe202b716
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/984393
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tell the base to hibernate when we are in S5, and no AC is connected.
Also, wake the base when AC status changes (S5), and when the system
transistions out of S5.
BRANCH=none
BUG=b:71874971
TEST=1. Lid EC console: apshutdown => Check that Base EC hibernates
2.a. Lid EC console: powerb; => Check that base reconnects
2.b. Connect/disconnect adapter: check that base disconnects
and reconnects
Change-Id: I5e9a4afc64a07ad92f37d171a78a914d26f07c8e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958814
Reviewed-by: Randall Spangler <rspangler@chromium.org>
MODULE_UART should be used for console UART, and MODULE_USART for
all secondary ones (like EC-EC side channel).
BRANCH=none
BUG=b:66575472
TEST=Flash wand, EC-EC communication works
Change-Id: I241bad7902c2e7228783ae1aa9cc33ad5da2c8a2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/958813
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
CONFIG_VSTORE is needed as a part of the verified boot process. When
the AP boots up, it hashes its FW and asks the EC to store this hash.
When resuming, the AP will ask the EC for this hash.
Meowth and Zoombini were missing this option which was a reason why
resume was failing.
This CL simply enables the VSTORE module and adds 1 VSTORE slot.
BUG=b:72472969
BRANCH=None
TEST=With updated AP FW with HAVE_ACPI_RESUME, verify that
suspend/resume works.
Change-Id: I07d0ce3ef426dc1924de6085703a4174f353f83d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/982598
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Tested-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
