2 Commits

Author	SHA1	Message	Date
Vincent Palatin	ba98b92bbb	cortex-m0: add more constraints on atomic implementation ... In ARMv6-m instruction set, the load/store address register can only be a "low" register : r0..r7. Update the inline assembly constraints to match the hardware. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd Reviewed-on: https://chromium-review.googlesource.com/224582 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>	2014-10-21 22:44:53 +00:00
Vincent Palatin	0f73a129b4	Add Cortex-M0 core support ... The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>	2014-03-11 05:52:41 +00:00