In some cases, the system will boot to S0 from the point of view of
the EC, but PLTRST# will never deassert. Work around this by waiting
50 ms for PLTRST# to deassert. If it doesn't, force the chipset all
the way down by deasserting RSMRST#, then pulse the power button to
turn it back on.
Also add a powerfail debug command to simulate this failure event, so
that the recovery process can be tested.
Add API to the LPC module to get the state of PLTRST#, and to the
power button state machine to force it released when we shut down the
chipset and and force another power button pulse as we reset the
chipset.
BUG=chrome-os-partner:28422
BRANCH=baytrail
TEST=1. Boot system. Should boot normally. Shut system down.
2. powerfail
3. Boot system. On the EC console, should see the system come up,
go back down through G3S5, then come back up. From the user's
point of view, it just boots.
1. Boot system. Should boot normally. (That is, powerfail is not sticky)
Change-Id: Ia57f196606f79b9f2fce7d9cd109ab932c3571aa
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197523
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add i8042 output port commands (0xf0-0xff), I8042_ENABLE_A20 and
I8042_DISABLE_A20.
BUG=chrome-os-partner:13119,
BRANCH=None
TEST=Tested on W7 installer. No KB error shown on EC console.
Change-Id: I9ad1fd7baa10683ef18ccf13faf09dc0cefcca0a
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/34994
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tidied comments, and removed handling of ACPI events on host command
port (not needed since EVT hardware is now EOL'd).
BUG=chrome-os-partner:15579
BRANCH=none
TEST='ectool hello' succeeds
Change-Id: I063382b9981f713ba23f7714b4ccb7faa957b411
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36804
Now both copies of the event state live in host_event_commands.c, and
lpc / memmap just shadows the main copy.
BUG=chrome-os-partner:11172
TEST=manual
Boot system. should see events 0x2000, 0x80, 0x08 get set and then cleared.
At U-boot prompt, type on keyboard. Should set event 0x1000 get set,
but only on the first keypress (because U-boot doesn't consume that
event).
Then from EC console,
hostevent clear 0x1000 -> see event 0x1000 clear
hostevent clear 0x1000 -> no debug output (it's already clear)
hostevent clearb 0x1000 -> see event copy B 0x1000 clear
hostevent clearb 0x1000 -> no debug output (copy B is already clear)
Change-Id: I855c035865649ba1490cd9027157d5bcdcc9895f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/27321
The phenomenon is that there is a char on-hold in port 0x60 and the kernel
never picks it up. Hence the keyboard cannnot be recognized after resume.
It comes from multiple reasons:
1. The command I8042_CMD_RESET_BAT(0xff) and I8042_CMD_ENABLE(0xf4) didn't
clean the buffer.
2. clean_underlying_buffer() has clean the queue, but forgot to clean the
TOH (TO Host). Add keyboard_clean_buffer() to clean the TOH (To Host).
3. When KB interrupt is just enabled, the IRQ didn't sent if there is
a char queued in buffer already. keyboard_resume_interrupt() solves
this.
4. Not all keyboard reset should reset the buffer. Only the enable/disble
of controller RAM should NOT reset buffer. Other enable/disable
should clean the buffer.
5. i8042 commands (those commands to port 0x64) should NOT return ACK
even the parameter byte(s) goes to port 0x60.
6. Keyboard was disabled by kernel, but key stroke still sent to host
(this needs the BIOS to fix).
Also fix the minor issues:
1. I8042_CMD_RESEND should not return I8042_RET_ACK.
2. I8042_DIS_KB/I8042_ENA_KB should effect the controller RAM content.
3. only send out the scan code when keyboard is enabled.
4. add kblog command for future debug (disabled by default because it
neeeds 1KB of memory).
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:9525
TEST=tested on link. Start from S0.
1. Run powerd_suspend.
2. Expect system is in S3.
3. Press any key to wake up system.
4. Expect system is up and keyboard is working.
5. repeat for 20+ times.
Change-Id: I1c48822687d7c1f7ef0e8d8bca54bf9b05fd785f
Preparatory work to use common host command code between ARM and x86.
Every command sends back explicitly the size of the response payload.
The size of the response defaults to 0 ond can be updated.
Add a protocol version number returned as command 0x00 to help with
backward compatibility.
move a couple of function from lpc specific header to host commands to
be able to implement them for the I2C link.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9614
TEST=make BOARD=link
Change-Id: I6a28edf02996ddf6b7f32a3831d07d5f0271848f
This covers modules which need to initialize before task_start(), but
don't particularly care in what order they're initialized.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=if it boots, it works
Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
This is necessary to support SCI/SMI events.
Note that this breaks compatibility with previous ectool builds - and
probably also breaks flashrom support.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8253
TEST='ectool hello' and 'ectool flashinfo' still work
and 'ectool usbchargemode 3 1' fails with error 2
Change-Id: If39e5b6e7cdcec1b5ec765594e8492925b430b10
This will allow more efficient access to EC-provided data (temperature,
fan, battery) by the main processor.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7857
TEST='ectool hello' from link main processor should still work
Change-Id: I2dc683f3441b34de9fb4debf772e386b9fdcfa82
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7488
TEST=type things into the x86 console UART; should appear on the u-boot prompt
Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
The problem comes from the different assumption of interrupt mode in EC and
the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge.
However, the auto-IRQ functino of EC is level-triggered and uses low-active to
assert an IRQ. This makes the deadlock so that the kernel never gets an
interrupt until a byte is manually pulled from host.
So, the solution is manually firing an IRQ_1 to host after EC puts a byte to
port 0x60. Note that the auto IRQ needs to be disabled in order to avoid
the interference with manual IRQ generation.
This CL also moves chip specific code to lm4/lpc.c and handle some minor
keyboard commands.
BUG=none
TEST=on hacked baord.
Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
LPC module no longer directly talks to UART registers, and vice-versa.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='ectool sertest' on target system
Change-Id: Id070c0d849bdfe91c752e0af651d357b695d2648
(cherry picked from commit ab8c3c2b8e3b08a4bf5573cda3a12dd3a384e67d)
