The cros_ec_debugfs creates the `console_log` debugfs entry if EC
supports EC_CMD_CONSOLE_READ version 1. On device where i2c command
latency is critical, periodic console_read is impacting the timing of
commands.
BRANCH=none
BUG=b:37584134
TEST=on rose with CONFIG_CONSOLE_ENABLE_READ_V1 undefined, the kernel
should not create cros_tp/console_log.
Change-Id: I40d0b959ef36f2f410155fa30e01c8169032a3e9
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/494546
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Add new host command EC_CMD_RWSIG_ACTION for controlling rwsig task.
This allow us to make firmware stay at RO without toggling reset pin.
flashrom can use this host command and removed the need to use any
out-of-band pin to toggle the reset pin (and make RWSIG stay in RO).
BRANCH=none
BUG=b:37584134
TEST=on eve, `ectool --name=cros_tp rwsigaction abort` should prevent EC
from jumpping to RW after RWSIG check.
Change-Id: Ia435e4e3ea8ed612a1250d3bf755ca50e5db9d37
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497787
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This CL added the support for the quasi-bidirectional buffer which has
an open-drain output and a low-impedance pull-up resistance on KSO pins.
The low-impedance pull-up is active when ec changes the output data
buffers from 0 to 1, thereby reducing the low-to-high transition time.
Add CONFIG_KEYBOARD_KSO_HIGH_DRIVE to enable/disable this feature for
npcx7 series ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
Change-Id: I138f0e433394816e1e5c58b5053580f202c1ac48
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497189
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL added the support for additional 5 adc channels on npcx7 series
ec. The pin-mux functionality of adc channels was already introduced in
CL 481561.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 10 adc channels passed the test on npcx796f evb.
Change-Id: I2c7458958ff659fce78f265eefa160050dee7daf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497526
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since a04fc68e72 "usb_i2c: refactor into common", the code in
chip/stm32/usb_i2c.* is dead, let's remove it to avoid confusion.
BRANCH=none
BUG=b:35578857
TEST=On hammer, userspace application can still talk to trackpad.
Change-Id: Idd9cc1109c80f3949fa8c4e50f4fe2e267d5a7ae
Reviewed-on: https://chromium-review.googlesource.com/492768
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
First, improve debounce logic to only notify AP on base detection
change.
Then, handle side-band signals. For that purpose, base EC pulses
detection pin for 100 us to signal out of band USB wake (that
can be used to wake system from deep S3). We filter these, and
only consider a single ~100us during a debounce interval to be
a valid out-of-band signal.
BRANCH=none
BUG=b:35775062
TEST=Flash hammer and poppy, connect them together. Put poppy in
deep S3 (powerd_dbus_suspend), hammer can wake poppy on
key press.
TEST=Change hammer's board_usb_wake to send invalid pulses (too long,
too short, multiple pulses within 5ms), and see that all those
pulses are ignored.
TEST=Check that PP3300_DX_BASE is 0 when base is not connected,
and 1 when it is connected.
Change-Id: I20bf4151134099f52fe8fe0332524aa1ca5f7d63
Reviewed-on: https://chromium-review.googlesource.com/490130
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This CL added support for 8 i2c controllers and 11 i2c ports in
npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions
related to chip family to them. (Such as i2c_port_to_controller(),
i2c_select_port() and so on.) Note the layout and bit position of i2c
registers which are accessed in these functions are irregular between
npcx5 and npcx7. We think abstracting them from i2c.c is easier to
maintain.
In this CL, we also modified the checking rule for I2C_PORT_COUNT in
task.h in order to prevent compiler error. So far, the ECs besides
stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes
its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule
for all ECs seems not suitable.
It also includes
1. Remove useless NPCX_I2C_PUBIT macro function.
2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h.
3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c
controllers of npcx7 ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed
i2c stress tests on npcx796f evb.
Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/487541
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This mode had to be disabled for P1 because of leakages on PP3300_A
that affected the voltage levels on the CC lines. With EVT the leakage
issues have been resolved and now this feature can be enabled.
BUG=b:35648532
BRANCH=none
TEST=With lidopen attached sink only adapter to port 1. Then executed
'lidclose' via the EC console and verified that the port went into low
power mode as expected. In addition, without adapter connected,
verified that when in low power mode the EC console was not flooded
with low power messages.
Change-Id: I281497cc6fe251d48c4ea737c7b4242200d39421
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/496947
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Create an app to extract relevant information
from the EC code base that's used to create Vendor
Information Files (VIFs) needed for USB Type-C
compliance testing.
BUG=chromium:701852
BRANCH=none
TEST=make -j buildall
Compared generated VIFs to expected values
Change-Id: I600ca78b9fb5d2de78aa65a58264c6f79b36ea17
Reviewed-on: https://chromium-review.googlesource.com/455280
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch clears the typematic buffer when disabling keyboard scan.
When the device goes to tablet mode with a key being pressed, this
should prevent keyboard_protocol_task from sending scan codes to the
host.
BUG=b:35585725
BRANCH=none
TEST=make buildall. Tested on Electro.
Change-Id: I73e9d2948b472458814967307412aebeb410ff2e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/425075
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EVT introduced the Simplo A50 battery pack so need to add this to the
list of possible Eve battery types.
The precharge current level of the battery type is used to set both
the trickle charge and precharge current levels on the Rohm bd9995x
charger. Rohm is advising that this value be set to 256 mA. What we
observe is that when the charge has to operate in buck mode, that the
previous setting of 64 mA is too low. The value of 88 mA was required
for the Lishen P1 pack to no trip it's overcurrent limit in precharge
mode.
BUG=b:37291519
BRANCH=none
TEST=Manual With battery pack at low (~4.2 V), connect blackcat
charger and verified that the battery begins to charge. Without the
precharge current level change, the battery would never charge unless
VBUS was set to 5V.
Change-Id: Iad155de63c6ad4b342791d7024c44fa208b76ab8
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/494080
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
The function bc12_detect was using a msleep(312) to allow for enough
time for the bd9995 to determine the charger type. Putting the USB_CHG
task to sleep for this period of time means that the USB_CHG task is
not able to process interrupts from the bd9995 during that time. This
is a particular problem when Try.SRC is enabled and a charger is
connected. VBUS will only remain present for ~40-50 msec, and
when it goes away, the discharge circuit should be engaged. However,
the USB_CHG task is still in the 312 mSec sleep from when VBUS was
detected. The result is that discharge circuit is not engaged. It was
observed that processing of charger interrupts could be delayed
upwards of 500 msec.
On Eve with the EVT charger, VBUS was not discharging without the
discharge circuit being enabled. This resulted in excessive connect
time as the Try.SRC cycle repeated many times until a case where the
discharge circuit was not disabled when VBUS detect occurred and this
finally allowed the charger to attach.
This CL modifies the USB_CHG task main loop so that a wait timer is
used when bc12_type needs to be read from the charger. There is a wait
timer mark per port. If the mark value is 0, then a wait timer is not
required and the task is put to sleep with -1. Each time the task is
woken, either from the interrupt or wait event timer, the current time
is checked against the timer mark for each port. The function that
reads the bc12_type will return a 1 if the type is still not available
and will return 0 if either VBUS is no longer present, or the
bc12_type was successfully determined.
With this change in place the discharge circuit is reliably
enabled/disabled within ~5-10 mSec of VBUS changes.
BUG=b:37292010
BRANCH=reef,gru
TEST=Manual
Added signal probe wires to VBUS, discharge control, and charger
interrupt signals. Connected eve EVT charger and verified that the
discharge circuit is consitently enabled when VBUS is removed
following the initial attach in Try.SRC. Verifed that the EVT charger
always connects on the first attempt.
Also tested with various different chargers on both Eve and Reef
platforms. In addition, temporarily changed the initial deferred time
to 100 mSec and validated the path where vbus_provided is not true and
that additional deferred calls were initiated until bc12_type is valid.
Change-Id: Idd066b5461ec4cbb77bb023519fed90c9e9f71db
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/487028
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Update GPIO pinout for poppy rev1. The incompatible changes
are gated with #ifdef POPPY_REV1, which can be set in board.h.
For soraka, rev1 is the default.
For poppy, we'll switch the default board revision at a later stage.
BRANCH=none
BUG=b:35585396
TEST=Build and boot poppy and soraka on poppy-rev0, still works fine.
Change-Id: Iaca1721f38566848cd725dbc396d93e4913de0d7
Reviewed-on: https://chromium-review.googlesource.com/481564
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Default mux to A on power on. This allows charge
on idle or unconfigured systems so the device won't
run out of batteries while idle.
BRANCH=None
BUG=b:37542705
TEST=reboot tigertail. Device charges through port A.
Change-Id: I4f12629978fd06c8ea781330243abbbaea7efe4b
Reviewed-on: https://chromium-review.googlesource.com/493922
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When usb_wake is called (key press, trackpad event), pulse
detection pin for 100us. This allows Lid EC to wake the AP
even when it is in deep S3 mode, where normal wake using USB
lines does not work.
BRANCH=none
BUG=b:35775062
TEST=Flash hammer, looks at poppy console: base power is not
disconnected, but events appear in the console.
Change-Id: I7b8ee407046d4caa1ce75190c30d693b71b00d2e
Reviewed-on: https://chromium-review.googlesource.com/448380
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Augmented PDOs are part of the PD3.0 specification. As present USB PD
sinks can't support these PDO types we need to ignore them.
BRANCH=samus,glados,oak,gru,reef
BUG=b:37476637
TEST=manual,
On samus, plug-in blackcat (EVT) charger and see it ignore these
Augmented PDOs when making its PDO request.
Change-Id: I28a0377e1486368f25f37cad640af71244a4c30b
Reviewed-on: https://chromium-review.googlesource.com/484687
Commit-Ready: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Current usb_wake was sleeping between setting and clearing RESUME
bit, which is unprecise.
Instead, we count ESOF interrupts in usb_interrupt to detect when
to clear RESUME.
It is also important that usb_wake does not block, as the calling
task (e.g. keyboard scanning) must continue to service events while
the USB device is resuming.
BRANCH=none
BUG=b:35587173
TEST=Connect hammer, force autosuspend using:
DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct))
echo 500 > $DEVICE/power/autosuspend_delay_ms
echo auto > $DEVICE/power/control
Wait a second, type something quickly, verify that no keys are lost.
Change-Id: I53b46cce5a4adb0ee4c4a7e9f935c00f7f321636
Reviewed-on: https://chromium-review.googlesource.com/490129
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If user holds down volume up, volume down and power button for 30
seconds, set HW_REINIT event and blink LED for 3 seconds to indicate
to user that the request was accepted.
BUG=b:37682514
BRANCH=None
TEST=make -j buildall
Change-Id: I6b70d56f50d0a1cfae3fa7f337a34ac487943775
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/487281
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Provide led_control API that can be used by different drivers to
control the state of LED (0=off, 1=on, 2=reset)
2. Add a new LED ID for recovery HW_REINIT indication.
BUG=b:37682514
BRANCH=None
TEST=make -j buildall
Change-Id: I27334bde2b879046746456a610208f3fc2dd68b4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/487840
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If volume up + volume down + power buttons are held down for 30
seconds, then indicate to AP that HW_REINIT is requested by the
user. Since recovery mode is triggered by holding down the three buttons
for 10 seconds, button_check_hw_reinit_required checks for 20 more
seconds only.
BUG=b:37682514
BRANCH=None
TEST=Verified that:
1. If volume up, volume down and power are held for 30 seconds, AP
sees the hw reinit request.
2. If either of the buttons is released before 30 seconds, AP does not
see the hw reinit request.
Change-Id: I3a53966dcdcb84d73f160578411b6c0f62225b95
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/487002
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The usb_updater code comparing versions to decide which one is newer
filters out values in excess of 1000 to not consider dev build
versions to be newer than the released versions.
In fact this logic is flawed: with node locked RO it is possible to
build dev (self signed) version, which can run on the device, and this
version should take over the released version, if it is currently
present on the device.
If the RO is not node locked, the dev RW version will not verify, so
it is safe to download it to the chip, it would be ignored.
BRANCH=cr50
BUG=none
TEST=with this patch applied it is possible to update self signed
versions running on H1 (the updater considers them newer than
0.0.18 and sends the chip the vendor command to enable the
downloaded image after download completes).
Change-Id: Ibb5761e4bb24fcc7dee5cc10b2f26af7a8e9aa2e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/492087
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The node locked ROs expect the RW image to be self signed with a 2048
bit key.
The only case where loader-testkey-A.pem file is used is is building
vanilla images which can't even run any more (they used to be good
for old dev RO). Let's replace the 3072 bit key with a 2048 bit key
generated by running
'openssl genrsa -3 2048 > util/signer/loader-testkey-A.pem'
BRANCH=none
BUG=none
TEST=verified that RW signed with this key can be run by a node locked
RO.
Change-Id: I74d189d03acb663fde7db48815e54748163c6399
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/489434
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
1. Disable USB debug interface:
If we don't use GPIOH.5/6 pins for debugging,
we should disable it to prevent any chances of entering debug mode.
2. command_idle_stats() behind CONFIG_CMD_IDLE_STATS:
We can exclude this console command if we don't use it.
3. Remove 'dsleep' console command:
DEEP_SLEEP_ALLOWED macro is enough for us.
BRANCH=none
BUG=none
TEST=bit7 at 0xF02030(MCCR register) is cleared after initialization.
Change-Id: If34e9738351459891be8c9a6619384adbfe26335
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487843
Reviewed-by: Randall Spangler <rspangler@chromium.org>
AP will use that command to tell base EC that it believe the current
FW is functionning correctly, and that the rollback region can
be unlocked for an update on the next reboot.
BRANCH=none
BUG=b:35586219
BUG=b:35587171
TEST=- Flash hammer ToT image with rollback version 0
> flashwp true; reboot
> flashinfo => all flash is protected
- Update CONFIG_ROLLBACK_VERSION to 1
$ make BOARD=hammer -j
- Flash new RW
$ sudo extra/usb_updater/usb_updater2 -w
$ sudo extra/usb_updater/usb_updater2 -r
$ sleep 0.5
$ sudo extra/usb_updater/usb_updater2 -s
$ sudo extra/usb_updater/usb_updater2 build/hammer/ec.bin
> rollbackinfo
rollback minimum version: 0
RW rollback version: 1
- Tell RW to unprotect rollback
$ sudo extra/usb_updater/usb_updater2 -u
$ sudo extra/usb_updater/usb_updater2 -r
> rollbackinfo
rollback minimum version: 1
RW rollback version: 1
Change-Id: Ib52253e9b8bba872688d6f601d9bfad8862be25f
Reviewed-on: https://chromium-review.googlesource.com/489889
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Starting with
be294d4ef "hammer: Only define required options for RO and RW"
we do not define CONFIG_RWSIG for the RW section. However,
we want CMD_UNLOCK_RW to be usable when EC is in RW section, to
unlock itself in prevision for an update on the next reboot.
BRANCH=none
BUG=b:35587171
TEST=Update hammer using usb_updater2
Change-Id: I7ae001363697bc3e17d4a59b21413d35101228cb
Reviewed-on: https://chromium-review.googlesource.com/489888
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The existing commands do not really need longer response code.
Future commands can always reply with more data as needed.
BRANCH=none
BUG=b:35587171
TEST=Update hammer using usb_updater2
Change-Id: I37cb8ac444d58216a7d98c9090043b06d95c74e1
Reviewed-on: https://chromium-review.googlesource.com/489887
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, usb_port_power_dumb allows fixed number of ports (2)
and usb_port_power_smart allows less than 4 ports. This change
removes the limitation and makes them accept variable number of
ports.
BUG=chromium:715178
BRANCH=none
TEST=Verified usbchargemode returns consistent charge_mode across
sysjumps on Electro.
Change-Id: I7675c65ba03d3e6f7f53b2fe48cbe510231d945a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481077
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is useful for debugging, to understand if the RW rollback
version is ahead of current rollback version.
BRANCH=none
BUG=b:35586219
TEST=Flash hammer, rollbackinfo in EC console
Change-Id: I2634199845f1b35447e0938a35b862f79cb24ffa
Reviewed-on: https://chromium-review.googlesource.com/489886
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We can get the correct chip info after the change was made.
BRANCH=none
BUG=none
TEST=console message:
[0.013915 TCPC p1 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec]
[0.018054 TCPC p0 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec]
Change-Id: I4eb94967acb351559e745ed1c4e34a4c58f41e14
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/487767
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The virtual battery "energy" readings were totally broken. Rather
than reporting things in units of "10 mW" they were reporting things
in units of "10 uW". That's because they were doing this math:
result = mV * mA / 10
Said another way:
result = (V / 1000) * (A / 1000) / 10
result = (V * A) / (100000) / 10
result = W / 1000000 / 10
result = uW / 10
Aside from the fact that clients were expecting things in "10 mW"
instead of "10 uW", we got even more random results. That's because
we return to the client in a 16-bit variable, so we were kinda
randomly truncating things.
Doh.
BRANCH=ToT
BUG=chromium:717304
TEST=power_supply_info
Unfortunately when you try to report sane values for "10 uA" in a
16-bit result, it doesn't work too well (
Change-Id: I8075dffd7ab6b372be5b8fdf293acc96c5878036
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/492546
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 01ceab68cd6b542f8c6355425e6ac6da698e0ebf)
Reviewed-on: https://chromium-review.googlesource.com/492568
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
This change is separated from CL:344481.
We need a cold reset after flashing, but we kill 'servod' before
execute iteflash for each flashing process.
With this change, we can restart 'servod' again without errors.
And we are able to use dut-control to do a EC cold reset.
BRANCH=none
BUG=none
TEST=flashing completed, and wait for servo's cold reset.
Change-Id: Ifc242467211253fabcd733a971e999baa68a1026
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/488002
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If charging current is set to 0mA during charging, reference of
charge current feedback amp (VREF_CHG) is set to 0V. Hence the DCDC
stops switching (because of the EA offset). To eliminate this issue,
disable/enable charger depending on the charging current is zero
or non-zero respectively.
BUG=b:37413065
BRANCH=reef
TEST=test 'ectool chargecontrol normal/idle/discharge' are working
Change-Id: Id31876afe365a476fb906e059ab519b7a0c9a7c6
Signed-off-by: james_chao <james_chao@asus.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/486101
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 6da9ed8786e90ee91b39934180fe84e01ac30260)
Reviewed-on: https://chromium-review.googlesource.com/489812
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
According to the new MCU secure update model, EC should wait for host if
reset source is reset-pin.
BRANCH=none
BUG=b:37584134
TEST=on rose, toggle reset pin from host. EC should stay in RO, showing
[0.426089 Hard pin-reset detected, disable RW jump]
in console.
Change-Id: Ie1908cb0744773e2e3ca8b3d8c627b8a9ef4567f
Reviewed-on: https://chromium-review.googlesource.com/485199
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add a new host command EC_CMD_RWSIG_CHECK_STATUS for getting rwsig
status and rw firmware hash. This command is used to check the RW
signature of newly updated RW image.
A new subcommand is also added to ectool.
BRANCH=none
BUG=b:37584134
TEST=on rose board `ectool rwsigstatus` works
Change-Id: I33d8709f5248d3a4b8bedb36ded84a93dc8c971f
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/485079
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Poppy should be able to use the low power idle mode for the npcx EC
to get lower power in S3, and in S5 before we enter hibernate.
BUG=b:36372576
BRANCH=none
TEST=build and boot on poppy (with HW VBUS rework and HACK CLs),
enter S3 or S5 and observe, using idlestats, that dsleep gets
enabled after the 15 second console idle timeout.
Change-Id: Ide656711ef87313aec396e34284982b77040dc23
Reviewed-on: https://chromium-review.googlesource.com/487921
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Split i2c.c code in two (i2c_slave.c and i2c_master.c). i2c_slave.c is
used when EC has no i2c device connected (i2c master code not needed)
but EC is connected to AP via i2c.
BRANCH=none
BUG=b:37584134
TEST=1. Compile rose board with CONFIG_I2C and CONFIG_CMD_HOSTCMD. Then
make sure EC_CMD_GET_PROTOCOL_INFO works.
2. On Kevin and Elm, cherry-pick to firmware branch respectively,
build and flash ec, i2c function works.
Change-Id: I1f95ad277713c5e30913e0a010ca03dfd9ec248c
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/484999
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rose reads heatmap via halfduplex SPI sensors. This change fixed the
macro to get correct DMA ISR register.
BUG=chromium:688979
TEST=manually run spixfer in EC console and check return value
BRANCH=none
Change-Id: I303bdb483032c02d01fd322095f17dba37555447
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444631
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There is a window where the rollback information in RW could
potentially be updated during RW signature verification. We make
sure this cannot happen by:
- Preventing update over USB while RWSIG is running
- When system is locked, only update rollback information if
RW region is locked: this guarantees that RW cannot be modified
from boot until RW is validated, and then until rollback
information is updated.
Also, remove rollback_lock() in rwsig_check_signature:
rwsig_jump_now() protects all flash, which also protects rollback.
This reduces the number of required reboots on rollback update.
BRANCH=none
BUG=b:35586219
BUG=b:35587171
TEST=Add long delay in rwsig_check_signature, make sure EC cannot
be updated while verification is in progress.
Change-Id: I7a51fad8a64b7e258b3a7e15d75b3dab64ce1c94
Reviewed-on: https://chromium-review.googlesource.com/479176
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On "normal" EC, we do protect RW as part of software sync, which would
call flash_command_protect (which indirectly calls flash_protect_at_boot).
Here, we don't want to (and can't) rely on the host to tell us to protect
the RW, so we need to protect it ourselves before jumping to RW.
This does feel a little redundant with rollback_lock though, since ALL
will protect both RW and ROLLBACK: a later CL will fix that up.
BRANCH=none
BUG=b:35587171
TEST=flashwp true; reboot; RO protects all flash before booting to RW
Change-Id: I820cabb01d1ca4aa47b81fc013a1670134a6be09
Reviewed-on: https://chromium-review.googlesource.com/476453
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add support for 4 extra commands that are required to update
hammer:
- UPDATE_EXTRA_CMD_IMMEDIATE_RESET
- UPDATE_EXTRA_CMD_JUMP_TO_RW: Tells the RWSIG task to jump
to RW as soon as possible (assuming the image verifies)
- UPDATE_EXTRA_CMD_STAY_IN_RO: Tells the RWSIG task to not
jump to RW, and stay in RO, to leave enough time for
AP to update RW.
- UPDATE_EXTRA_CMD_UNLOCK_RW: Tells EC to unlock the RW
section so that it can be updated (on next reboot).
BRANCH=none
BUG=b:35587171
TEST=Test RO+RW update
cd extra/usb_updater; make
# Jump to RW
sudo ./usb_updater2 -j
sleep 0.5
# Update RO, then reboot
sudo ./usb_updater2 ../../build/hammer/ec.bin
sleep 0.5
# Update RW (first tell RO to not jump to RW)
sudo ./usb_updater2 -s
sudo ./usb_updater2 ../../build/hammer/ec.bin
TEST=Test RW update only, with RO protected
On EC console: flashwp true; reboot
cd extra/usb_updater; make
# Tell RW to unprotect RW and jump back to RO
sudo ./usb_updater2 -w
sudo ./usb_updater2 -r
sleep 0.5
# Update RW, then reboot
sudo ./usb_updater2 -s
sudo ./usb_updater2 ../../build/hammer/ec.bin
Change-Id: I5e8df7bdb4f06f2ac7b47de53dcde69c5002f578
Reviewed-on: https://chromium-review.googlesource.com/458470
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
On npcx5, the peci speed should be 750K bps but we got 1.5M bps since
selecting wrong source clock of peci. From the peci specification, the
speed range is from 2K bps to 2M bps. That's why we still passed the
peci test on npcx5's evb. This CL corrects the source clock of it from
apb2 to fmclk and make sure the speed is 750K bps by the scope.
BRANCH=none
BUG=none
TEST=Passed peci test on npcx5's evb and make sure the speed of peci is
750K bps.
Change-Id: Ic5c55f7be9be195182e4c4f4ad64b7426afd42db
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/486680
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
