Updating the fan speeds according to the manufacturer's specs.
The fan vendor recommends that the minimum fan speed be a 20%
duty cycle. Since the built-in fan controller has a tach-based
feedback loop, I'm using the RPM value instead of the duty cycle
(20% is 2286 RPM, according to the vendor).
The vendor also wants a 30% duty cycle to start turning, but the
built-in fan controller provides support for fast-start too. The
controller's minimum fast-start duty cycle is 50%, but it also
has a programmable number of revolutions that it will wait before
backing off.
Holding my ear down close to the fans while they start and stop,
it seems that the minimum 2 revolution start period is sufficient
and provides the least noise. Of course, since I've never had any
problems starting the fans directly at 1000 RPM this noise is a
little more noticeable than that. It's quite possible that the
built-in controller is smart enough to make 1000 RPM work by
bumping the duty cycle up until the fans turn even if the fans
don't like it.
BUG=chrome-os-partner:32892
BRANCH=ToT,samus
TEST=manual
Listen closely and run the EC console "faninfo" command to see
the fans start and stop as the system boots and idles.
Change-Id: I47c9e7cef3f9f4bd815a13032fe10234decd62ed
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224830
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Integrate charge_manager and include several API changes designed
for reporting voltage.
1. Make pd_choose_voltage set the chosen voltage for use by caller.
2. Add voltage parameter to pd_set_input_current.
3. Add pd_get_role to grab the sync / source state of a port.
4. Add charge manager PD + type C port initialization to the pd
state machine.
BUG=chrome-os-partner:32003
TEST=Manual on samus. Insert Apple charger, verify charge limit is
selected appropriately. Insert PD charger, verify that charge port
switches to PD port. Remove + reinsert chargers, verify that port /
limit is selected appropriately. Remove battery, insert power source, verify
that our power source port never becomes disabled.
BRANCH=samus
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Idf3198c71d2ddf1e401e766fc82a4b7a02aed068
Reviewed-on: https://chromium-review.googlesource.com/223758
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Unlike STM32F0, we need to configure alternate function for USB module
on STM32F373. Adds the pin configuration for ryu_p2 and also adds the
proper configuration step in USB module.
BRANCH=None
BUG=chrome-os-partner:32660
TEST=With changes to enable USB on ryu_p2, see the device enumerated
Change-Id: I5e2cb7cfc44a1bb88bae69804021c783c8d17968
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224789
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Ryu uses the same LEDs as Samus, so let's use the same brightness values
for them. Also, increase the stack size for console task so that
'lightbar' command doesn't cause stack overflow.
BRANCH=None
BUG=chrome-os-partner:32203
TEST=See lightbar in action on Ryu.
Change-Id: I89b61f6df2751c9dd6b40f9e374f01e1b0dfd504
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224426
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The new build target ryu_p2 is mostly based on ryu. On ryu_p2, we have a
new EC chip with bigger flash, so make the corresponding changes:
- Pinout changes
- HW Timer: TIM5
- USB PD Tx Timer: TIM3_CH4
- USB PD Rx Timer: TIM2_CH4
- Use UART2 for EC console
- Disable UART Tx DMA as it conflicts with USB PD Tx DMA
- Use 24MHz HSE x2 = 48MHz for SYSCLK
BRANCH=None
BUG=chrome-os-partner:32660
TEST=Sanity check on a new board:
- i2cscan
- PD negotiation
- UART console
- gettime
Change-Id: I4ef6b53a928a2777721e3874032aeb0e6b2b4c92
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221404
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The original algorithm is given in the TMP006 User's Guide
(SBOU107.pdf). The algorithm we previously implemented is that,
plus some additional and completely undocumented massaging of the
Tdie and Vobj registers. The original meaning of that hack is now
lost in the mists of time, thanks to our email retention policy.
This CL introduces a new algorithm variant, but at least this
time the details are in the bug report. It's essentially the same
as the User's Guide algorithm, except that we apply one-stage FIR
filters to the Tdie input and the Tobj output.
There are five new parameters: d0, d1, ds, e0, e1. Refer to
tmp006_read_object_temp_k() in ec/driver/temp_sensor/tmp006.c to
see how these new parameters are applied.
CAUTION: The tmp006 sensor algorithm is mostly math and magic
numbers. The spreadsheet attached to the bug report has six
sheets with wildly varying values for those parameters. Since the
correct parameter values haven't yet been determined for Samus,
all I can be sure of with this CL is that it seems to work and
isn't any worse than the old one.
Oh, and note that the EC's 't6cal' console command has been
disabled until/unless we add support for floating point IO. Use
ectool from the host to get and set the params instead.
BUG=chrome-os-partner:32260
BRANCH=ToT,Samus
TEST=manual
After booting, look at the sensor values using ectool:
localhost ~ # ectool temps all
0: 312
1: 314
2: 313
Sensor 3 not calibrated
4: 311
Sensor 5 not calibrated
6: 305
Sensor 7 not calibrated
8: 306
Sensor 9 not calibrated
10: 307
Sensor 11 not calibrated
12: 312
Sensor 13 not calibrated
localhost ~ #
localhost ~ # ectool tempsinfo all
0: 0 PECI
1: 1 ECInternal
2: 1 I2C-Charger-Die
3: 2 I2C-Charger-Object
4: 1 I2C-CPU-Die
5: 2 I2C-CPU-Object
6: 1 I2C-Left C-Die
7: 2 I2C-Left C-Object
8: 1 I2C-Right C-Die
9: 2 I2C-Right C-Object
10: 1 I2C-Right D-Die
11: 2 I2C-Right D-Object
12: 1 I2C-Left D-Die
13: 2 I2C-Left D-Object
EC result 2 (ERROR)
...
localhost ~ #
There are six tmp006 object temps that need calibrating. The
index used for the calibration is for the tmp006 objects, not the
3,5,7,.. numbers reported for all temp sensors. See the current
values with tmp006cal:
localhost ~ # /tmp/ectool tmp006cal 5
algorithm: 1
params:
s0 0.000000e+00
a1 1.750000e-03
a2 -1.678000e-05
b0 -2.940000e-05
b1 -5.700000e-07
b2 4.630000e-09
c2 1.340000e+01
d0 2.000000e-01
d1 8.000000e-01
ds 1.480000e-04
e0 1.000000e-01
e1 9.000000e-01
localhost ~ #
If the s0 param is zero, this sensor is uncalibrated. The params
are entered in the order in which they're displayed You can
change any or all of the parameters. Skip the ones you don't want
to update by specifying '-' for its position. (Note: throw in an
extra '--' first so that ectool doesn't think that negative
numbers are command options).
For example, to change s0 and b0:
localhost ~ # ectool -- tmp006cal 5 1.0 - - -3.0
localhost ~ #
localhost ~ # ectool tmp006cal 5
algorithm: 1
params:
s0 1.000000e+00
a1 1.750000e-03
a2 -1.678000e-05
b0 -3.000000e+00
b1 -5.700000e-07
b2 4.630000e-09
c2 1.340000e+01
d0 2.000000e-01
d1 8.000000e-01
ds 1.480000e-04
e0 1.000000e-01
e1 9.000000e-01
localhost ~ #
Now sensor 13 (tmp006 object index 5) is calibrated:
localhost ~ # ectool temps all
0: 310
1: 315
2: 313
Sensor 3 not calibrated
4: 310
Sensor 5 not calibrated
6: 305
Sensor 7 not calibrated
8: 307
Sensor 9 not calibrated
10: 307
Sensor 11 not calibrated
12: 312
13: 313
Change-Id: I61b5da486f5e053a028c533ca9e00b9a82a91615
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224409
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add macro for default hibernate delay, and set to 7 days on samus.
Also, adds CONFIG_ option for hibernating early if low on battery.
For samus, setting early hibernate at 1 day when battery < 10%.
BUG=chrome-os-partner:33088
BRANCH=samus
TEST=make buildall
Added ccprintf("Target shutdown: %.6ld\n", target_time); to print
out target shutdown time after setting it. Verifed the following
on samus
1) If CONFIG_HIBERNATE_DELAY_SEC is left at default 3600 (samus
board.h does not overwrite it), then target time is 3600s.
2) If CONFIG_HIBERNATE_DELAY_SEC is defined in samus/board.h, then
target time equals that value.
3) If CONFIG_HIBERNATE_DELAY_SEC is defined as 1 week and
CONFIG_HIBERNATE_BATT_PCT is defined to 10% and
CONFIG_HIBERNATE_BATT_SEC is 1 day, then when battery is between 8-10%
target time is 1 day and if battery is at 11%, target time is 1 week.
Change-Id: Ief155ad6c327775fa348d3458fc47ee9dd8569c3
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Per revisements to the DisplayPort Alternate mode specification there
are two additional SVDMs for DPout support: status & configure.
This CL adds those SVDMs and calls them (status then config) after
finding a device that supports DP Alternate mode.
Future CLs will use these SVDMs to complete providing HPD over CC
support.
BRANCH=none
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual, plug hoho/dingdong into samus and see:
1. Additional DP status [16] & DP configure [17]
2. Drives DPout properly
Change-Id: I52b373085ddc330e4afb1d1883d2621bc2e4ee95
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223260
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
All non-interactive console prints should use their tasks channel
parameter to make it easy for developers to inhibit console output.
This CL corrects printf's in the various usb_pd_policy files that
belong to the USB PD task to use cprintf(CC_USBPD, ...) instead of the
macro reserved for interactive console commands ccprintf.
BRANCH=none
BUG=none
TEST=manual, set 'chan 1' and see none of the previous chatter
relating to USB PD. set 'chan 0x08000000' and see it return.
Output from DFP side for SVDM discovery now looks:
SVDM/4 [1] ff008041 340018d1 00000000 11000008
[1119.966911 DONE]
SVDM/2 [2] ff008042 ff010000
[1119.970135 DONE]
SVDM/2 [3] ff018043 00100081
[1119.973437 DONE]
SVDM/1 [4] ff018184
Change-Id: I47e5f4ec2d4a6a25f171177ead5ebc99409f80b6
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224191
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
So far, we always use channel 1 of the Tx timer and the configuration
code is hard coded. We need to support other channels for new Ryu
boards. Let's make this a configurable bit.
BRANCH=samus
BUG=chrome-os-partner:32660
TEST=make buildall
TEST=Plug in Zinger to Ryu and see 20V come up.
Change-Id: Id08d4eb0d6a5721d8a03672484d0892a0714383b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223836
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previous reading of specification left some doubt about how SVDM
responder to 'discover modes' command communicated the number of valid
modes. It is communicated via the 'object position' field in the VDM
header where: opos = modes + 1.
This change adds the mode count to the opos field and sends only that
amount of data back to the initiator. Initiator stores that mode_cnt
so that it can correctly choose a mode when 'enter mode' phase occurs.
BRANCH=none
BUG=chrome-os-partner:30645
TEST=manual,
1. see SVDM responder to Discover modes only send supported number of
modes for SVID.
2. 'pe 0 dump' displays correct set of discovered modes on initiator.
Change-Id: I9b626dd6dd3e85e80b4f0596332300d74b1830ee
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223981
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Original implementation was complicated by belief that we'd want PD
MCU to manage entry of multiple alternate modes. This simply won't be
practical given the upper level system policies that would need to
weigh in on these decisions as well as the seemingly endless additions
to the alternate mode ecosystem.
Longer term we'll need to pass the generic alternate mode discovery
VDO info to the kernel/userland to implement remainder of policy.
However, for short term lets implement single mode entry instead.
BRANCH=none
BUG=chrome-os-partner:30645
TEST=manual, mode entry is successful on both ports.
Change-Id: Ia24f5ee4d59c13c62d68b30f8587b5e5fbdb2fa0
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223980
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
- Remove hardware double-buffering : it's complex to get right and does
not provide any performance improvement.
- Increase buffer size x2 to decrease overflow frequency.
- Fix buffering and simplify code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28337
TEST=make BOARD=twinkie
do a long acquisition on a sample pattern from the function generator
and verify that no packet are missing and the waveform looks good.
Change-Id: I12a9e8370d3f238e8894f15ce0190e2e0fbc26d7
Reviewed-on: https://chromium-review.googlesource.com/223565
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
The register format of INA231 and INA219 are very much alike. In our
use case, we only need to use different coversion coefficient.
BRANCH=None
BUG=chrome-os-partner:32764
TEST='ina 0' on Plankton V2.
TEST=Build twinkie.
Change-Id: I9c8e21e30ed844566793dcc1221f865400c3d90d
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223370
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Adds double tap detection for samus. When user double taps
in S3 or lower to show battery state of charge on lightbar.
BUG=chrome-os-partner:29041
BRANCH=samus
TEST=make buildall
Tap the lid in S3 or lower.
Change-Id: Ic5f4709bdee2472cb7e91717318337b04bae1fc8
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221965
Reviewed-by: David Schneider <dnschneid@chromium.org>
When the cable flip button is pressed, instead of only flipping on
Plankton side, we should also signal the port partner to flip. This is
done by sending a custom VDM. Upon receiving the flip VDM, the port
partner is responsible of flipping the DP/USB polarity.
Note that the "flip" here only affects the superspeed lanes. The CC
lines polarity is not changed. We need this for factory test automation,
and this "flip" function should only be used for testing purpose as it
clearly violates the USB PD spec and it only works on devices that
accept the custom flip VDM.
BRANCH=Samus
BUG=chrome-os-partner:32163
TEST=COnnect Plankton and Ryu. Press the button on Plankton and make
sure the polarity GPIOs on Ryu are negated.
Change-Id: I7ee5ea70067de4f422a7478623fe7fe8d3724372
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223325
Reviewed-by: Alec Berg <alecaberg@chromium.org>
VCORE needs time to come up after PCH_PWROK is asserted and we
should be waiting for VCORE_PGOOD to be 1 before proceeding.
This also moves the 5ms delay for PCIe to be before SYS_PWROK
since that is where it is requried according to the power
sequence specification (rev 1.3 figure 2-4).
BUG=chrome-os-partner:33027
BRANCH=samus
TEST=build and boot on samus
Change-Id: I4bd969bdb56ecf14cc68754318452861b70f0539
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224033
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Enable hibernate on zinger for DVT. Note: this may break
some EVT zingers.
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=make buildall
Hibernate tested in CL:220837
Change-Id: I65f4776d27ad88beee101fb00d0b6221ba272a26
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
USB PD spec now calls for HPD signal to be managed across the USB PD
protocal. In preparation this CL makes the HPD GPIOs outputs and
initially low.
This should NOT effect older revs of the design as GPIOs were unused
(had unstuffed option for external XTAL).
BRANCH=samus
BUG=chrome-os-partner:30645
TEST=compiles & runs. With reworked board can manually trigger HPD.
Change-Id: I0a64c1daf8d8c866f5de237c3daf4be028eecd63
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223462
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The ADC interrupt does not clear the NVIC pending register. This
can cause the interrupt to fire more than once for a given
interrupt.
BUG=none
BRANCH=samus
TEST=Send hard reset from samus to zinger using "pd 1 hard" on
PD MCU console. This causes zinger to cut its output voltage
and go into voltage discharging mode. When voltage discharge is
complete, we get an ADC interrupt and switch back to current
monitoring. Before this CL, sometimes (1 out of 20) times the
ADC interrupt will fire twice, causing an OCP to be detected.
With this CL, we never see the double fire.
Change-Id: I91397a04773d04e263bc80a698c8799342b80a2e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223381
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PD task is using more space in the stack and I'm seeing frequent
stack overflow on Plankton. On Samus, we already increased the stack
size. Let's also increase this on Ryu and Plankton.
BUG=None
TEST=make buildall
BRANCH=None
Change-Id: I468985303b7fd38455dd1fed9db54544581c49cf
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223368
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Display battery percentage on the lightbar whenever AC status
changes.
BUG=chrome-os-partner:32894
BRANCH=samus
TEST=Plug and unplug AC in S0 and in G3 and make sure that lightbar
displays battery percentage each time
Change-Id: I281c9242d185da06b0c778de12e4f6340779a840
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223362
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add support for enabling Vconn on Raiden ports by defining
CONFIG_USBC_VCONN. This is enabled by default for ryu, samus,
and fruitpie.
BUG=chrome-os-partner:30445
BRANCH=samus
TEST=Load onto samus. Make sure we can still charge from zinger.
Plug in type-A to type-C adapter with pulldown and see that samus
becomes power source. Do a gpioget and verify that only one VCONN
GPIO is enabled (low), and the VCONN that is enabled is opposite of
the polarity queried by pd 1 state. Try both ports, both polarities
and make sure the correct VCONN gpio is enabled.
Change-Id: Icea4c18b9c813cf7e8e21fd4f455bbd5fb4dbc91
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222850
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Per alternate mode this GPIO should not be enabled until alternate
mode has been successfully entered.
BRANCH=none
BUG=chrome-os-partner:31192
TEST=manual, compile & boot on hoho gpioget PD_SBU_ENABLE = 0
Change-Id: Ide2a47851f30812b289221e302a930134a58a8a0
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223159
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move the 3.3DSW_GATED rail to be enabled in transition to S0 and
disabled in the transition to S3.
This is the rail for the core regulator and temp sensors so it
does not need to be enabled in S5.
BUG=chrome-os-partner:32382
BRANCH=samus
TEST=build and boot on samus, successfully suspend/resume and
ensure that PP3300_DSW_GATED is turned off in S3.
Change-Id: Ic47f81860e3f0cb7b5d81ba96181b7ee7cf72f66
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223077
Reviewed-by: Alec Berg <alecaberg@chromium.org>
There's already an external pull-up to PP3300. The internal pull-up has
no use but provides a leakage path when the AP is off.
BUG=chrome-os-partner:31762
TEST=Repeatedly power cycle Ryu. Check the system goes to S0/S5.
TEST=Power off from the AP. Check the system goes to S5.
BRANCH=None
Change-Id: Id0ae966414de01e3a2b91314f661f37941175a87
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Wire up the discovery's four LEDs and one user
button as GPIOs that can be written and read using
the new USB GPIO driver. This also adds an extra
tool called usb_gpio that provides control of GPIOs
from the linux command line.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=cd board/discovery-stm32f072 ; make flash
cd extra/usb_gpio ; make
usb_gpio write 0x1e 0x00
Change-Id: I15115f82b15b6c35d1a34b83b7114a6bfa6a3d67
Reviewed-on: https://chromium-review.googlesource.com/218270
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Remove the meaningless version string in iSerialNumber, which was incorrect
since this string should be unique to a device if it exists.
Export the firmware version string as the configuration string, so it's
traceable to a given firmware build/sources.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=make buildall
from a workstation, do "sudo lsusb -v" and see the full version string
exported as the configuration name.
Change-Id: I557df2936421e2926ac0fc0003888370cec3e201
Reviewed-on: https://chromium-review.googlesource.com/222877
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Add a compile-time configuration to make Twinkie behave as
a USB Power Delivery consumer/provider device rather than a
transparent sniffer.
To use it, edit board/twinkie/ec.tasklist:
enable the PD task and comment out the SNIFFER task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=connect it to a Fruitpie and use "pd charger" command on Twinkie
console, see the Fruitpie receiving the source capabilities and
answering.
Change-Id: Ic2b4ba2d166ea1d3f5f9be410453a030a4ee7b68
Reviewed-on: https://chromium-review.googlesource.com/204168
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Change effects:
1. samus_pd: Acts as initiator of SVDM discovery once its reaches source
ready and upon identifying UFP with display port
alternate mode enters that mode.
2. hoho: Acts as responder for SVDM discovery providing its identity,
svids and svid capabilities which are display port only. If
asked to enter display port alternate mode it does.
3. fruitpie: Acts a initiator with mock display port mode.
BRANCH=none
BUG=chrome-os-partner:30645
TEST=manual,
Plug hoho into samus_pd
- see dpout
- from console
> typec 0
Port C0: CC1 451 mV CC2 111 mV (polarity:CC1)
Superspeed DP1
Change-Id: I1a76767353a69baeceffa3e79c37dcea77b8337d
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221354
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some platforms may need to take different actions depending on which
port is requesting a limit. Add a new port parameter to the
pd_set_input_current_limit API to accomodate this.
BUG=chrome-os-partner:32003
TEST=Manual on samus_pd. Verify zinger charges battery.
BRANCH=samus
Change-Id: I1578252c751b3a80b4da6ca68e2a958934283cbf
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222621
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add support for enabling USB type-C Vconn by defining CONFIG_USBC_VCONN.
Enable Vconn support for samus, ryu, and fruitpie.
BUG=chrome-os-partner:30445
BRANCH=samus
TEST=make buildall
Change-Id: Ibe247286c96fd5a8fa12c88a4e3a5fea02997134
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222284
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PD protocol no longer uses a SHA1 RW hash. Instead, it uses the
first 20 bytes of the SHA-256 hash. Update constants and comments
accordingly.
BUG=chrome-os-partner:31361
TEST='make buildall -j'
BRANCH=samus
Change-Id: Ice74b841dbd1d81205c1ef0079a5e18fca2153b6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222446
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This lowers the CPU temp at which the fans start up, from 55C to
43C. It also increases the slope a bit, so that they run a little
faster as well.
BUG=chrome-os-partner:32260
BRANCH=ToT,samus
TEST=manual
Visit www.fishgl.com/?full both before and after this CL.
Before, the keyboard got a little too warm. After, the fans come
on sooner and the keyboard is cooler.
Change-Id: I5c4947c5d2bb4a28c0ac449e109e2bd1af84068c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222171
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Allows dingdong to receive initial USB PD communication (source
capabilities payload) and with some manual manipulation (see 'TEST=')
drive DPout.
CL is based heavily off hoho dongle where all files were copied from
board/hoho:
7b1e58c ectool: Add host command support to set fan RPM for each
fan separately
Files gpio.inc, board.h & board.c were modified but others should
be identical.
BRANCH=none
BUG=chrome-os-partner:31193
TEST=manual,
When attaching dingdong to samus_pd and configured via
'pd dualrole source'
I see following on samus_pd console:
C1 st9
Switch to 5000 V 900 mA (for 900/900 mA)
C1 st10
C1 st11
C1 st12
showing power constract and transition to SRC_RDY:
> pd 1 state
Port C1, Enabled - Role: SRC Polarity: CC1 State: SRC_READY
> typec 1 dp
Also if I connect in CC1 configuration and get access to dingdong
console I can
> gpioset PD_SBU_ENABLE 1
And see dingdong drive external monitor
Change-Id: I30ef6f8503a3fb015cfb8806bc36fb98f5150e40
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Fix bug that can cause ADC initialization to hang and eventually
watchdog. Problem was that you need at least 4 ADC clock cycles
between end of ADC calibration and enabling ADC (setting ADEN).
Fix is to (1) move some ADC configuration to between end of cal
and setting ADEN, and then just to be safe, (2) continually set
ADEN until we see ADRDY (ADC ready).
See bug report for more information.
BUG=chrome-os-partner:32561
BRANCH=samus
TEST=load onto a samus that regularly has ADC problems on boot.
Using power+refresh verify that without this change PD hangs
some of the time, and with this change it never hangs.
Change-Id: Ifa4c3240ad7e1612647cc74e2105e6545ed19db4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221984
Reviewed-by: Vic Yang <victoryang@chromium.org>
Design Goals:
1. Every time the AP boots, the same default sensor settings are configured.
2. If the AP goes to suspend (S3) and wakes back up (S0),
then the AP sensor settings will be restored.
3. In S3 and in S5, only sample specific sensors that are needed.
BUG=chrome-os-partner:32368
BRANCH=ToT
TEST=Verified on Samus.
Verified suspend and resume logic with EC console messages.
- Test Case0: close lid & open lid
- Test Case1: powerd_dbus_suspend
Change-Id: I553c53e63ecfcb39d5e649a7189aa6ea02589471
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/220371
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Seems that all previous boards used the subvariant specific name, and had an
alias from emerge-variant_subvariant to the ec subvariant folder.
BUG=chrome-os-partner:32331
BRANCH=None
TEST=cd board/pinky; make clean && make -j && ../../util/flash_ec --board=pinky
Change-Id: Ie6e0c977b6659687357a1b5aa2915cf0e40a5da7
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add a minor revision to the PD device hardware ID field in the info
custom VDM and set increment this minor ID from 0 to 1 for zinger.
This differentiates zingers for the auto-update payload, so we can
update only those with a specific major and minor ID version.
BUG=none
BRANCH=samus
TEST=load onto samus and zinger. when connect zinger, see on PD
console: Dev:0x0401 SW:2289 RW:0, which shows the appropriate
device ID.
Change-Id: I482ee2d850332b608cdd81537f68d4dc509bfc1a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221320
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
