flash_ec is used for both ec chips accessed over servo, and
standalone stm32 devices. It's not necessary to have a servo
conencted to update the standalone devices over usb.
This is useful for servo v4 and servo micro.
BUG=chromium:571477
TEST=Verify servo micro/discovery can be flashed without servo v2.
BRANCH=none
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I9deee1616d93feeac4d6675bc3a4f573d4906f7b
Reviewed-on: https://chromium-review.googlesource.com/321925
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@google.com>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Updated the permissions of ec_uart_pty to match the permissions of the
other PTYs.
BUG=None
BRANCH=None
TEST=cros_workon hdctools ec-devutils, run servod, ls -l on ec_uart_pty
from dut-control, verify that permissions are 666.
Change-Id: I71c72645c5a435fea562084185b80ff6d31652b4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321371
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
This commit adds support for the EC-3PO interpreter to disconnect and
reconnect to the EC UART. This is handy so that other tools that need
to use the raw UART directly can do so without interference from
EC-3PO.
BUG=chromium:571170
BRANCH=None
TEST=For both enhanced and non-enhanced EC images, issue disconnect
command and verify that no debug prints were emitted and no commands
were sent to the EC. Then issue reconnect and verify that the console
works as normal and that no commands were buffered.
TEST=./util/ec3po/run_tests.sh
Change-Id: Ic572e25d24d5e45fbe2eeb84a534235c4ec98d38
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321084
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If a user had already run util/ec3po/run_tests.sh, and then never
modified any ec3po files, the presubmit check would list every file in
the EC repo that was newer since the the last run. This included
files such as build artifacts.
BUG=chromium:575032
BRANCH=None
TEST=Run ./util/ec3po/run_tests.sh once. Run make -j buildall, try to
upload and verify that no nag message to run ec3po tests is presented.
TEST=Touch an ec3po file, try to upload, verify that nag message about
running ec3po unit tests is presented.
Change-Id: I4f09bb76dcd85b570b57030197f4887bed85f1a7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321134
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The presubmit check would nag at the user to run the EC-3PO unit
tests, even if they hadn't modified any EC-3PO files. This was not my
intention. This commit fixes the presubmit check to only check for
unit test success if a EC-3PO file is modified.
BUG=chromium:575032
BRANCH=None
TEST=Remove util/ec3po/.tests-passed; Modify a non-ec3po file, commit,
and try to upload. Verify that no nag message is presented.
TEST=Remove util/ec3po/.tests-passed; Modify a ec3po file, commit, and
try to upload. Verify that a nag message to run unit tests is
presented.
Change-Id: I86e9f325329b7ad1a4c7c5971b7851e9024e7750
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/320831
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Some devices have multiple ECs (main EC and PD MCU) and therefore there
are multiple consoles and interpreters running concurrently. This
commit prepends each log message with the served PTY to identify which
of the console or interpreter instances the log message comes from.
BUG=None
BRANCH=None
TEST=Ran ec3po in servo for samus. Noticed each debug print with the
different PTYs for the main EC as well as the PD MCU.
TEST=util/ec3po/run_tests.sh
Change-Id: Icc69d2257172f4fedc217572ad0b6d15dac40387
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/320597
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
In testing, it was found that certain ECs couldn't respond to the EC_SYN
in less than 0.1s. Therefore, this commit changes the interrogation
timeouts. For non-enhanced EC images, the timeout has been increased to
0.3 seconds. This is small enough that there's not too much of a delay,
but long enough that enhanced EC images can respond in time. With an
enhanced EC image on veyron_jerry, EC_ACKs were arriving after ~0.2s.
BUG=None
BRANCH=None
TEST=Flash enhanced EC image on veyron_jerry, start console/interpreter
pair and verify that the console is functional.
TEST=util/ec3po/run_tests.sh
Change-Id: I4931aaee908653ae302a8e57941444e5f0b6ce2b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/320594
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added presubmit check to make sure that when any ec3po files are
modified, the unit tests should be run as well.
BUG=None
BRANCH=None
TEST=Touched a unit test file, tried repo upload and received an error
about running unit tests. Ran run_tests.sh and all tests passed. Tried
to repo upload again and this time it succeeded.
TEST=Created a failure in one unit test, ran run_tests.sh and verified
that the failure was caught and the CL wouldn't pass the presubmit
check.
Change-Id: I4df4a0fd1107292f693749188491f6286360f557
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/319211
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ecst is used at build / link time, so it should be compiled for the
build machine architecture, not the architecture of the host board.
BUG=chromium:567232
TEST=Verify 'cros_sdk ... cros_run_unit_tests --board=oak' passes with
CL:319256.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic7f6aa989d0760eda1fe64221e41d3230c9ab9b9
Reviewed-on: https://chromium-review.googlesource.com/319633
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The console and interpreter are usually killed by KeyboardInterrupt
whether or not it's run standalone or by servod. This commit tries to
make the exit graceful by closing pipes, file descriptors, and exiting
each process.
BUG=chromium:570526
BRANCH=None
TEST=Run ec3po standalone and hit Ctrl+C to kill it. Observe no
traceback and no leftover processes.
TEST=Repeat above test, but inside servod
TEST=cros lint --debug util/ec3po/console.py
TEST=cros lint --debug util/ec3po/interpreter.py
TEST=python2 -b util/ec3po/console_interpreter.py
TEST=python2 -b util/ec3po/console_interpreter.py
Change-Id: Ia151b9ede8adf7f8dec6c07277f62d097c13e63e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/319252
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
This commit adds a setup script for the ec3po package. This is
necessary such that ec3po can be included as a part of ec-devutils.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=Update the ec-devutils ebuild to install the ec3po package.
sudo emerge ec-devutils; `python -c 'import ec3po'; print ec3po`
in the chroot. Verify that ec3po is installed in the site-packages.
TEST=Verify that interpreter and console modules are exported in the
package.
CQ-DEPEND=CL:316479
Change-Id: I5c8856b530936dc4ce3b09e38802f1e015c4576b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316701
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
It was brought to my attention that there were some issues with the
ec3po code. This commit addresses those issues raised.
- executable bits dropped from __init__.py and interpreter.py.
- sys.argv[1:] is now passed into console.py:main().
- Added blank lines at top of header.
- Removed dummy exception class (MoveCursorError).
- Added name of modules in the logger, so that it's not just 'root'
when included in other modules.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=./util/ec3po/console_unittest.py -b
TEST=./util/ec3po/interpreter_unittest.py -b
TEST=cros lint --debug ./util/ec3po/console.py
TEST=cros lint --debug ./util/ec3po/console_unittest.py
TEST=cros lint --debug ./util/ec3po/interpreter.py
TEST=cros lint --debug ./util/ec3po/interpreter_unittest.py
Change-Id: I00db368906958d1089c3662eb253be23f81cc70c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316479
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Newer versions of glibc have moved to _DEFAULT_SOURCE and away from
_BSD_SOURCE. Trying to use the BSD define by itself leads to warnings
which causes build failures.
BRANCH=none
BUG=None
TEST=precq still works
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Change-Id: Ice24b84dc6a540695fc7b76e8f22a4c85c301976
Reviewed-on: https://chromium-review.googlesource.com/316730
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The EC-3PO console and interpreter could be used to talk to EC images
which do not have the necessary changes to support the new enhancements.
If this was the case, the interpreter would be very confused and the
user wouldn't be able to use the console. This commit adds
compatibility support for talking to both non-enhanced and enhanced EC
images.
When the console and interpreter are instantiated, they assume by
default that the EC image they are talking to is non-enhanced. When the
user presses the carriage return key, the console initiates an
interrogation with the EC image. The interrogation is a simple
EC_SYN(0xEC) and waits EC_INTERROGATION_TIMEOUT for the correct
EC_ACK(0xC0). Enhanced EC images will try to reply immediately to a
EC_SYN. Non-enhanced EC images will just ignore the EC_SYN as it's not a
printable character. Once the interrogation is complete, the console
will either simply pass everything forwards to the EC or provide the
console interface itself.
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Enabled CONFIG_EXPERIMENTAL_CONSOLE on GLaDOS. Entered some
commands and verified console was working. Disabled
CONFIG_EXPERIMENTAL_CONSOLE on GLaDOS, reflashed, and verified console
was still working without restarting the EC-3PO console.
TEST=./util/ec3po/console_unittest.py -b
TEST=./util/ec3po/interpreter_unittest.py -b
TEST=cros lint --debug util/ec3po/console.py
TEST=cros lint --debug util/ec3po/console_unittest.py
TEST=cros lint --debug util/ec3po/interpreter.py
TEST=cros lint --debug util/ec3po/interpreter_unittest.py
Change-Id: I4f472afbdd7e898bee308c239b68ace0f4049842
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/313002
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added new host command to support returning lid angle.
New output from ectool:
System with lid angle support:
------------------------------------------
localhost ~ # ectool motionsense lid_angle
Lid angle: 72
System without lid angle support:
------------------------------------------
localhost ~ # ectool motionsense lid_angle
EC result 3 (INVALID_PARAM)
BUG=none
BRANCH=none
TEST=run "ectool motionsense lid_angle"
verify the value matches the physical lid angle position
Change-Id: I4179172c778f643640561e819216f7adfee679d2
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/313345
Reviewed-by: Shawn N <shawnn@chromium.org>
When flashing the STM32 chip, the flash_ec script stops the processes
which occupy the EC UART in order to avoid their interference. After
flashing, it asks these process to continue.
However, when running FAFT in the lab, the EC UART may be occupied by
servod for sending some EC commands per test requirements. The
flash_ec should not stop the servod; otherwise, all the following
dut-control commands will be failed.
So this change blacklists the process servod and init.
BRANCH=none
BUG=chromium:552073
TEST=Manual
Ran a FAFT test, e.g. firmware_FAFTSetup, which occupies EC UART.
Ran another process, e.g. minicom, which also occupies EC UART.
Ran the flash_ec: flash_ec --chip stm32 --image /tmp/ec.bin
Its output:
INFO: Using ec image : /tmp/ec.bin
INFO: ec UART pty : /dev/ttyO1
INFO: Flashing chip stm32.
INFO: Using serial flasher : /usr/bin/stm32mon
INFO: Sending SIGSTOP to process 2369!
INFO: Sending SIGSTOP to process 7949!
INFO: Skip stopping servod or init: process 1.
INFO: Skip stopping servod or init: process 639.
...
INFO: Restoring servo settings...
INFO: Sending SIGCONT to process 2369!
INFO: Sending SIGCONT to process 7949!
Change-Id: I4d72b7e2caf0ca2963bb9dee51764869e829c569
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313581
Commit-Ready: Wai-Hong Tam <waihong@chromium.org>
Tested-by: Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This common for all g based boards file should not be associated with
a single board.
BRANCH=none
BUG=none
TEST=the device still builds and boots.
Change-Id: I34c49a095abd8e49b492c318823dd8f56609fdc8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313631
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
A few minor changes, this is still a USB image, no dcrypto support.
BRANCH=none
BUG=none
TEST=built an image using the new description and signer files, booted
it on an fpga board:
> vers
Chip: g cr50 B1 20151118_11218
Board: 0
RO: cr50_v1.1.4081-c06cf49-dirty
RW:
Build: cr50_v1.1.4081-c06cf49-dirty 2015-11-20 09:56:03 vbendeb@eskimo.mtv.corp.google.com
>
Change-Id: I29bbaaa512ff604beb209a606acf19282331c96f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313630
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Currently, using flash_ec for mec1322 chips only
supports flashing from servo v2. Updated to work from
v3 as well. This is a resubmission.
BUG=chromium:554230
BRANCH=None
TEST=tested locally with beaglebone/cyan setup at my desk
Ran flash_ec --board=cyan --chip=mec1322
--image=/tmp/image.bin. Also ran with servov2.
Change-Id: Ia2a7edb577350cd4aa1c9835f24f4e3df2e508e2
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313053
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
The git author date usually reflects the time a CL was first pushed to
gerrit, not the time it lands to the tree. Therefore, the author date is
misleading when used as a timestamp. Use the git commit date instead.
BUG=chromium:554675
BRANCH=None
TEST=Cherry-pick CL:293345 and verify date stamp is today, not last
August.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4fb042d7a706fbb86897b3e383b3242602af242b
Reviewed-on: https://chromium-review.googlesource.com/313022
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Currently, using flash_ec for mec1322 chips only
supports flashing from servo v2. Updated to work from
v3 as well.
BUG=chromium:554230
BRANCH=None
TEST=tested locally with beaglebone/cyan setup at my desk
Ran flash_ec --board=cyan --chip=mec1322
--image=/tmp/image.bin
Change-Id: Ibc1109a60e93d1034519b31ce58c5e4d45ab505c
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/312578
The code mixes up using of full flash addresses and flash segment
addresses (full address divided by 16). The vast majority of uses in
fact requires full addresses, but all definitions are using segment
addresses.
This patch converts definitions to full addresses, which improves
overall code readability.
BRANCH=none
BUG=none
TEST=verified that the signer signed image still boots properly on
CR50.
Change-Id: I35663c14357545c08ac1824d653c29cf6c4dda4d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311313
Reviewed-by: Nagendra Modadugu <ngm@google.com>
EC-3PO is the console interpreter that will one day replace the EC console
that we have today. EC-3PO aims to migrate our rich debug console from
the EC itself to the host. This allows us to maintain our rich debug
console without impacting our EC image sizes while also allowing us to
add new features.
This commit is the 1st of three phases, the insertion phase. The main
goal of this insertion phase is to get EC-3PO in place between servo and
the EC UART, while not modifying the behaviour of the console too
much. At this point, EC-3PO is capable of the following things:
- Replicate command editing.
- Save command history.
- Performs error checking with console commands.
The command editing should be at parity with the current EC console.
With EC-3PO, one can have a much longer command history which also
persists across EC reboots. And lastly, with a cooperating EC image,
EC-3PO can perform error checking with console commands. Automatically
retrying console commands if the command was incorrectly received at the
EC end.
Currently, commands are sent to the EC in a "packed" plaintext form.
The next phase will introduce the host command packet communication.
console.py is the module that provides the console interface between the
user and the interpreter. It handles the presentation of the console
including command editing.
It also has an accompanying set of unit tests in console_unittest.py.
It currently has 1 test suite to test the various console editing
methods.
interpreter.py is the module that provides the interpretation layer
between the EC and the user. It also is responsible for the automatic
command retrying. It requires pipe connections to be made to it for
command and debug data communication.
BUG=chrome-os-partner:46054
BRANCH=None
TEST=util/ec3po/console_unittest.py
TEST=Flash GLaDOS with a modified EC build. Run console.py passing the
EC UART, verify that I can edit commands, send commands, view command
history, and receive output from the EC.
TEST=cros lint --log-level debug ./util/ec3po/console.py
TEST=cros lint --log-level debug ./util/ec3po/interpreter.py
TEST=cros lint --log-level debug ./util/ec3po/console_unittest.py
Change-Id: I38ae425836efd69044334e1ed0daf3f88a95917c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/308615
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Add support for flash the ite ec from usb gpio port
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
BRANCH=none
BUG=none
TEST=Test OK on ITE8390CX from both GPIO PORT (C1,C2) (H5,H6)
You can run "make -j BOARD=it8380dev" to build ec.bin
and flash the ec.bin via
"sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin"
/* ==SNAPSHOT START== */
(cr) (br-iteflash) donald@donald-nb ~/trunk/src/platform/ec $ sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin
Waiting for the EC power-on sequence ...CHIPID 8390, CHIPVER 82, Flash size 256 kB
Done.
CHIPID 8390, CHIPVER 82, Flash size 256 kB
Erasing chip...
/100%
Writing 262144 bytes at 0x00000000
Done.
/* ==SNAPSHOT END== */
Change-Id: I422db6f7007622f8be624a534a482e24d53a061a
Reviewed-on: https://chromium-review.googlesource.com/311205
Commit-Ready: Donald Huang <donald.huang@ite.com.tw>
Tested-by: Donald Huang <donald.huang@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Donald Huang <donald.huang@ite.com.tw>
The signer running on the build host and the loader running on the
target must be in sync as of the structure of the signature header.
To be able to use the same definition in both programs, remove the
system includes from the .h file which needs to be shared. Rearrange
includes in image.cc to follow the coding conventions.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches applied the code successfully boots,
which indicates that the signer is in fact working properly. (See
the top patch for testing details).
Change-Id: I6bc9c57ebea55ac256fcdac8338c5566f16b6371
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311420
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This key is meant to be used by the RO image when verifying the RW.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches in place (in particular, this key's
public counterpart used in chip/g/load/verify.c), the RW is
successfully verified by RO.
Change-Id: Iddcc21d88518e402da614d20d913aeed162b0042
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311315
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When signer code was ported and enhanced to work with binaries (in
addition to hex), a bug was introduced, where the signed image is
considered to always to be based at the bottom of the flash. In fact
the image could be anywhere in the flash, the actual address derived
from the input elf file should be used.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=verified that when enabled, RW image is signed properly
(build/cr50/RW/ec.RW.flat starts with a signature).
Change-Id: I194bd02f932529165adcbebf4bcbd9020fc261dc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311314
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Register descriptions generate by the hardware tools always use the
block index when naming the base address of the bock, but the macros
compiling addresses out of register names do not use the index if
there is just one instance of the block in the design.
The problem is addresses by aliasing these definitions in registers.h
in the chip directory. This patch automates this aliasing and ensures
that the generated file has the aliases included, no need to add them
manually to registers.h.
BRANCH=none
BUG=none
TEST=re-generated cr50_regs.h, observed proper aliases created, built
and ran cr50 with the new registers file.
Change-Id: If037e082841a1510f7cad66737fd8b775dc667ea
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311371
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In fact this provides support for three FPGA images:
20151104_011218 - full crypto, no USB
20151104_041733 - tiny crypto, full USB
20151104_065845 - full crypto, full USB (only for hard-to-get boards)
We can tell these FPGA images apart at run-time by looking at
some SWDP registers:
register crypto usb full
GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135
GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3
This CL includes a run-time check for the USB features so that
it's safe to build the firmware with CONFIG_USB and run it on a
non-USB FPGA image.
Here are the differences I could find in the top-level image
header files:
All three FPGA images define different (apparently arbitrary)
default values for the PMU_PWRDN_SCRATCHn registers, but other
than that, the usb and full images differ only in the BUILD_TIME
and FPGA_CONFIG register values.
I'm not sure why, but function uart_init() in file
chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn
registers, but nothing seems to read it again.
The crypto image defines these values which don't appear in the
other images:
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52
#define PINMUX_USB0_EXT_RX_DMI_SEL 0x53
#define PINMUX_USB0_EXT_RX_DPI_SEL 0x54
#define PINMUX_USB0_EXT_RX_RCV_SEL 0x55
#define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56
#define PINMUX_USB0_EXT_TX_DMO_SEL 0x57
#define PINMUX_USB0_EXT_TX_DPO_SEL 0x58
#define PINMUX_USB0_EXT_TX_OEB_SEL 0x59
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230
#define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234
#define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238
#define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c
#define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240
#define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244
#define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248
#define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c
#define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250
#define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254
#define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0
#define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258
#define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0
The crypto image also differs in this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c
instead of this:
#define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230
The rest of the differences between the crypto and usb versions
are in these values, which I don't think we care about. At least,
I can't find any place where they're used.
PINMUX_EXITEDGE0_DIOAn_OFFSET
PINMUX_EXITEDGE0_DIOBn_OFFSET
PINMUX_EXITEDGE0_DIOMn_OFFSET
PINMUX_EXITEDGE0_VIOn_OFFSET
PINMUX_EXITEDGE0_OFFSET
PINMUX_EXITEN0_DIOAn_OFFSET
PINMUX_EXITEN0_DIOBn_OFFSET
PINMUX_EXITEN0_DIOMn_OFFSET
PINMUX_EXITEN0_VIOn_OFFSET
PINMUX_EXITEN0_OFFSET
PINMUX_EXITINV0_DIOAn_OFFSET
PINMUX_EXITINV0_DIOBn_OFFSET
PINMUX_EXITINV0_DIOMn_OFFSET
PINMUX_EXITINV0_VIOn_OFFSET
PINMUX_EXITINV0_OFFSET
PINMUX_HOLD_OFFSET
PINMUX_SEL_COUNT
PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL
PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET
PINMUX_XO0_TESTBUSn_SEL
PINMUX_XO0_TESTBUSn_SEL_OFFSET
I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h
BRANCH=none
BUG=chrome-os-partner:43791
CQ-DEPEND=CL:310978
TEST=make buildall
I also built a single Cr50 firmware and tried it on both the
crypto and usb FPGA images. Both worked as expected.
Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311211
Add support for two new configs to specify critical energy battery
percentage and critical external charger power. When we are under both
thresholds, set the LIMIT_POWER charger parameter to inform the AP that it
should conserve power to avoid brownout, and consider jumping to EC RW
to negotiate PD.
In addition, modify the existing CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
to allow power-up regardless of power level if a 15W+ charger is
attached, since there is a reasonable chance it may speak PD and provide
sufficient power to boot the AP.
BUG=chromium:537269
TEST=Manual on Glados. Set CHG_MW thresh to 20000, BAT_PCT to 50. Verify
that LIMIT_POWER charger param is set until Zinger negotiates to 20V. Also
veify that system can boot with Donette.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic963c82fea4ad10e8a5d7e476c5ce3e5ae525dad
Reviewed-on: https://chromium-review.googlesource.com/306774
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add chell_pd to the STM32 list and the USBPD override list.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=successfully run "flash_ec --board=chell_pd"
Change-Id: Ic4ddbe51a0586c563211fd76f20a85428e565546
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308726
Reviewed-by: Shawn N <shawnn@chromium.org>
FAFT and the lab infra calls the flash_ec by giving the chip name as
an argument, instead of the board name. The script should use the
chip name to check if it is a stm32 board.
BUG=chromium:546063
BRANCH=none
TEST=Call the script: flash_ec --chip stm32 --image /tmp/ec.bin
Change-Id: I8e9a029fb6e0aca5ea0f65876f48f6f465664c1c
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/307822
Commit-Ready: Wai-Hong Tam <waihong@chromium.org>
Tested-by: Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This enables support for a new FPGA image with tighter timing
constraints. Some USB functions perform better using this model.
There are also changes to the signing code.
BUG=chrome-os-partner:34893
BRANCH=none
TEST=make buildall
Change-Id: I608c2424d76b4ea566bf56fa0fed3810436216bb
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308063
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We've been converting the FPGA headers to our headers using a
script that we've passed around via email. Let's check it in so
we don't diverge.
BUG=none
BRANCH=none
TEST=manual
Run ./util/cr50_regs on the latest FPGA header, compare the
output with chip/g/cr50_fpga_regdefs.h. They match.
Change-Id: I6b435755a047265ea91d1af4e3e753e7555d149d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/306290
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch updates the EC codebase to match the suggested USB
build. The spiflash utility must come from the same tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
boot_rom 20151012_041715@75660
- booted the new image using the latest spiflash version. Note
that the bootrom now reports the FPGA image it comes from
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I4e21151d03d1050999ea2045b2be4b99886ff15c
Reviewed-on: https://chromium-review.googlesource.com/305260
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This patch updates the EC codebase to match the suggested USB
build. The spiflash utility must come from the same tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
BootRom 0.8.91hw
- booted the new image using the latest spiflash version. Note
that the bootrom now reports the FPGA image it comes from:
BootRom 20151007_064811@75052
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Iccd8f202493951f803393395273caa83467655df
Reviewed-on: https://chromium-review.googlesource.com/304622
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch updates the EC codebase to match the suggested USB build
(20151005_041713). The spiflash utility must come from the same
tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
BootRom 0.8.91hw
- booted the new image using the latest spiflash version.
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Change-Id: Iff778087149ae3e7570f8fd4d81c2857a4ea5367
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/304123
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This patch brings in the enhanced signer utility published along with
FPGA version 20150925_21715, and the image.cc file updated to fix the
bug where it was not picking up the initialized data segment from the
elf file.
The new signed image header format, among other things, describes
memory areas as read-only and read-execute, which allows the bootrom
to configure the MMU appropriately.
Makefiles had to be modified to reflect the fact that the signed image
now depends on .elf, not on .raw, and that building the signer
requires more source files. Note that some signer features are not yet
being utilized (like processing xml files describing fuses or
retrieving keys from gnubby), the source are kept for completeness.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=build the cr50 image and boot in on the FPGA board using the
spiflash utility outside chroot. Observe the target starting the
console session.
Change-Id: Ib59b8ebbeb98a8146d4d997e1f78178c4fbc031a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/303070
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This commit adds the "hibdelay" command which will set the time before
the EC hibernates.
BUG=chrome-os-partner:45608
BUG=chrome-os-partner:44831
BRANCH=None
TEST=Build and flash samus EC with hibernation delay host command
added. Use ectool to set the hibernation delay and verify that the
hibernation delay was changed.
CQ-DEPEND=302197
Change-Id: I91141ee48a648c1052f0a3930a810ea4f551e0a4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/302198
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
