Board rev0 will lose VBAT on power cycle and therefore
cannot successfully save the reset flag state.
Implement workaround that will allow these boards to continue to
work for FAFT testing by indicating to the skylake chipset power code
that it should skip the PMIC reset when doing 'reboot ap-off'.
BUG=b:63889675
BRANCH=None
TEST=None
Change-Id: Ie79053e2e52a3a9efd9cd864808af7214989602e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579666
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change makes EC run vboot in the HOOK task. The vboot routine
requires battery and charger info. It waits in a deferred call
loop until the charge manager is initialized.
BUG=b:63586051
BRANCH=none
TEST=Verify the following cases:
A. Hardware reboot (type-c/BJ)
1. Unplug AC in S0 then plug in AC: BOOT/BOOT
2. Unplug AC in S5 then plug in AC: S5/S5
3. Unplug AC after A.2 then plug in AC: S5/S5
4. Press PB in S5: BOOT/BOOT
B. Software reboot (type-c/BJ)
1. Run EC reboot command in S0: BOOT/BOOT
2. Run EC reboot command in S5: BOOT/BOOT
3. Run EC reboot ap-off command in S0: S5/S5
4. Run EC reboot ap-off command in S5: S5/S5
5. Run host reboot command: BOOT/BOOT
6. Run host shutdown command: S5/S5
C. Recovery tests
1. Press RB and PB in S0: FAIL(*1)/PASS
2. Press RB and PB in S5: FAIL(*1)/PASS(*2)
3. Unplug AC in S0 then press RB and plug in AC: PASS/PASS
4. Unplug AC in S5 then press RB and plug in AC: PASS(*2)/PASS(*2)
*1: b:63668669
*2: b:63669512. Requires one more PB press.
Change-Id: I28f37fdad7f83d0d44570b9003e8c6a4b83b832f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/568699
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch gives EC the capability of verifying and jumping to
RW_A or RW_B. EC tries the slot stored in a persistent storage
(e.g. BBRAM). If verification fails due to invalid contents, EC
tries the other slot. AP's expectation and its reaction to the
state of the slots and the currently running image are summarized
below.
Since the system is still unlocked (CONFIG_SYSTEM_UNLOCKED), EC
won't try to verify or jump to RW yet.
| AP expects X
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X' | reboot to B
SLOT_B=X | proceed
----------+---------------------------
SLOT_A=X | proceed
SLOT_B=X' | reboot to A
----------+---------------------------
SLOT_A=X' | write X to B, reboot to B
SLOT_B=X' | write X to A, reboot to A
BUG=b:38462249
BRANCH=none
TEST=Lock the system and boot Fizz on barrel-jack and type-c.
Change-Id: I51e3abd4d9af44ab3d531561cb9bfa2e8d775f6a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/556286
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit adds support for the PS8805, another Parade Tech TCPC with
integrated superspeed muxes. This also creates a generic Parade Tech
TCPC driver which supports the PS8xxx series.
The current supported TCPCs are:
- PS8751
- PS8805
BUG=b:63508740
BRANCH=None
TEST=`make -j buildall`
Change-Id: I78383af414996e0e8d6220985d286f95267136f8
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/564799
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
On a keyboard-less, volume-button-less board, we support simplified
sysrq handling.
For Fizz, we use the recovery button to trigger sysrq event and
holding it down to trigger warm reset.
BUG=b:38418116,b:38417391
BRANCH=none
TEST=On Fizz, try
1. Press recovery button and release -> sysrq sent
2. Press and hold recovery button -> warm reset
3. Press recovery button and power button -> enter recovery mode
Change-Id: If8760319dba3df4545e9805b396ac89c241dae80
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/537817
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds wait between DSW_PWROK and PWRBTN assert. It is
required to be 95 msec or longer for Kaby Lake and Sky Lake.
Refer to the timing diagram for G3 to S0 on Sky Lake or Kaby Lake
platform design guide for details.
BUG=b:62584658
BRANCH=none
TEST=On Fizz, measured time between DSW_PWROK high and PWRBTN assert
for 1:AC plug-in, 2:recovery+power press, 3: reboot ec command.
Change-Id: I89a14ac9a49e20a332bd662d90be62f8ea23b003
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/534901
The system power monitor function, aka. PSYS, of the ISL9238 chip
is disabled by default, this patch enables PSYS monitor in the
EC driver.
BUG=b:62041842
BRANCH=none
TEST=Able to read non-zero value at the MSR of
MSR_PLATFORM_ENERGY_STATUS (0x64D) by iotools;
Also, kernel powercap driver probes PSYS domain correctly;
Such that the kernel exports the sysfs node of intel-rapl:1
Change-Id: I7a533032815e873ae74dca42ec07041be0d0f975
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/520549
Tested-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This patch sets GPIO_LAN_PWR_EN to output/high to power on
the ethernet port at start.
BUG=b:37646105
BRANCH=none
TEST=Measured V3P3A_LAN is 3.3V.
Change-Id: I9629a72d1ffefd1ca2aeb8d2d1f5d74a953d7e58
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514622
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Fizz needs to set available power on type-c/pd before PD task starts.
PD task tries to reset available power at start-up. This patch prevents
those reset attempts from disabling already initialized power sources.
BUG=b:37316498
BRANCH=none
TEST=Boot Fizz on barrel jack and type-c adapters
Change-Id: I807f9d5ae4b4530fa80479b4e1a669569be841c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513582
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This change adds CONFIG_POWER_BUTTON_INIT_IDLE. When it's set,
the system starts with the power button state idle. It means
when the board boots from power-off, it stays at G3.
BUG=b:37536389
BRANCH=none
TEST=Power on Fizz. Verify it stays at G3. Verify it boots
by pressing power button.
Change-Id: I09a62a69d9f201b2dc261838cc9b4425fe3a8dc1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486945
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Fizz has two power sources: barrel jack and type-c port. It
selects a power source at boot and does not dynamicall switch
to the other ports after that.
Fizz initializes all power suppliers of all ports to zero then
initialize the source supplier (barrel jack or type-c port).
When both sources are provided, it prefers a barrel jack. This
detection is done by reading the voltage on PPVAR_PWR_IN.
If barrel jack is detected as a sink, type-c port works as a
source only. If type-c port is detected as a sink, type-c
port works as a sink only.
Fizz does not have a battery. So, battery module is removed.
BUG=b:37573548,b:37316498
BRANCH=none
TEST=Boot on both type-c & barrel jack.
Change-Id: If4f5ff0c6019d06ac9dacb5dd365f5aa96bffef3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/499547
This patch adds code to control the power LED.
BUG=b:37646390
BRANCH=none
TEST=Verify LED turns green, red, amber, off. Verify LED turns green
or off when chipset is on or off, respectively.
Change-Id: I1d7940d9bb4414d97c541ead802efeb8f279533e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486947
Cr50 masks the recovery button signal on a proto board when the
power button is being pressed (b:37682117). This bug has to be
fixed for the recovery button to work.
BUG=b:37274183
BRANCH=none
TEST=make buildall
Change-Id: Ia413ffce84d67b6f24f983ccce8ae8277452ac2c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This change makes Fizz enable USB type-A ports on resume and disable
them on shutdown.
BUG=b:38226666
BRANCH=none
TEST=Boot Fizz off of USB flash drive on a USB-A port.
Change-Id: I7f22438271ffc080e950f5f300937d89706e08a4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481078
This patch declares recovery_buttons array, where each board
lists recovery buttons. Pressing those while the board reboots
makes the system enter recovery mode.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I1f204156efbd6d2a507d67ba90f75ce857b03559
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486944
