If the sn5s330 PPC is being used to detect VBUS presence
(CONFIG_USB_PD_VBUS_DETECT_PPC), then enable interrupts and call
usb_charger_vbus_change when VBUS_GOOD changes.
BUG=b:72007153,b:72007492
BRANCH=none
TEST=Connect 3A and 1A USB-A chargers to each of Grunt's USB-C ports,
check that BC1.2 detection is working:
With 1A:
> chgsup
port=0/1, type=7, cur=500mA, vtg=5000mV, lsm=1
With 3A:
> chgsup
port=0/1, type=7, cur=2400mA, vtg=5000mV, lsm=1
TEST=Boot Grunt to OS, then connect USB2 mouse or USB3 flash drive to each
of Grunt's USB-C ports. Devices do not work due to b:71772180, but gpioget
shows EC is setting USB_C0/1_BC12_VBUS_ON_L correctly.
Change-Id: Iffc352105a321997adb364b9fbb8bafef248c224
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887938
Reviewed-by: Jett Rink <jettrink@chromium.org>
- Add a vendor command that provides alert counter. Userspace can use
it e.g. for user metric analysis.
- Add 'alerts' debug console command. It provides information about
chip alerts: supported alerts, fuse status, interrupt status, alert
counter.
- Add 'alerts fire [INT]' command to fire a software defined alert
(globalsec/fwN where N is 0,1,2,3).
Signed-off-by: Anatol Pomazau <anatol@google.com>
BUG=b:63523947
TEST=ran the FW at Pyro and checked alerts data sent to host
Change-Id: I7cec0c451ed71076b44dad14a151b147ff1337e8
Reviewed-on: https://chromium-review.googlesource.com/817639
Commit-Ready: Anatol Pomazau <anatol@google.com>
Tested-by: Anatol Pomazau <anatol@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This allows the acpi_light sysfs entry to be populated with the actual
ALS data.
BUG=b:70290036
BRANCH=None
TEST=Flash meowth; read both illuminance values for the ALS devices
under iio and verify that they are both operational.
Change-Id: Ia22633629195d5bdeedc70a908ceca1411110b7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/888218
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
It's no longer necessary to call board_tcpc_init() from PD tasks, since
HOOK_INIT completion is guaranteed before the task starts. Also, calling
board_tcpc_init() for each PD task without a port arg is a bad idea.
BUG=b:72229154
BRANCH=none
TEST=`make buildall -j`
Change-Id: I6fba07771693b8343568041960a263e02775a8fc
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/881538
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
stm32f0 has 20 bytes (not 20 words) of VBAT-backed RAM. Make more
efficient use of our limited storage to prevent trying to use storage
that doesn't exist.
BUG=b:71333840
BRANCH=None
TEST=Negotiate PD, run "reboot" on scarlet EC console, verify reset path
is taken in pd_partner_port_reset().
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie4c303b74a1b82b84ec971cdcc19c2b21a0032e7
Reviewed-on: https://chromium-review.googlesource.com/885461
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is required to support mode-aware DPTF. Also, there is no need to
send mode change event in board specific code as that is already done
by dptf common code.
BUG=b:65467566
BRANCH=None
TEST=Verified that trip point temperatures get updated in the OS
depending upon the device mode.
Change-Id: I854628bcde755bdb1c6c1b73fbfa0948e1d7e420
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887725
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add BOARD_DEEP_SLEEP_DISABLED and BOARD_DETECT_AP_WITH_UART to
BOARD_ALL_PROPERTIES, so they will be updated after cr50 reboots.
BUG=b:35647982
BRANCH=cr50
TEST=test deep sleep on scarlet
Change-Id: I8999ae7c6c1dad6799b5fdb99ebf5d7618a21c2b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/882343
Reviewed-by: Randall Spangler <rspangler@chromium.org>
First version of the algorithm, some TODOs are left in the code
but this, generally, works reasonably well.
When charging, we allocate input current in this general order:
- Base system (fixed, low, number)
- Lid system (based on PSYS)
- Lid battery (estimating how much current the battery actually
requires)
- Base battery (similar estimation)
- Provide everything else to lid
When discharging, we generally:
- First discharge the base battery
- Then discharge the lid battery
BRANCH=none
BUG=b:71881017
TEST=Flash lux and wand, EC-EC communication works, adapter power
is split in a sensible way, and discharging works fine.
Change-Id: I8a4f87963962fc5466b2fedf1347eb4dadd35740
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659460
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Lux base detection is a little trickier than previous bases,
as the detection levels switch around when GPIO_EC_COMM_PD gets
enabled:
- When disconnected, low levels (~550mV) mean base got connected,
and high levels (~3300mV) mean base is still disconnected.
- When connected, low levels (~43mV) mean base got disconnected,
and high levels (~2346mV) mean base is still connected.
On reset, when base_status is unknown, we enable GPIO_EC_COMM_PD,
to be able to differentiate between connected and disconnected.
BRANCH=none
BUG=b:67029560
TEST=Connect lux/wand, check that base gets detected correctly.
TEST=Type reboot in EC console, base gets detected as well.
Change-Id: I742def8e378a93c08e2dcc155b06cbca814e7fd8
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/845543
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The way Nautilus battery checks the conditions of CHG/DSG FETs
are slightly different from the other smart batteries we use.
So the current implementation of battery_check_disconnect() doesn't work.
BUG=b:69016914
BRANCH=none
TEST=recovery from software-based battery cutoff 10/10
Change-Id: I88de64d8da55f0b57fbdde21d4529435841bdf76
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/882941
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There are two versions of npcx7 EVB. This CL adds the definition
BOARD_VERSION (default is 2) in board.h. So we can include different
features or set CONFIG_* flags based on the value of BOARD_VERSION to
meet the default HW configuration of npcx7 EVBs.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change BOARD_VERSION to 1/2; "BOARD=npcx7_evb make";
Flash the image on EVB 1/2; make sure the EVBs bootup.
Change-Id: Id4556f702af8c26778a649addde7cf490b5301fc
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/873510
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To support CR50 deep sleep mode:
In up-sequence, SYS_RST_L needs to remain asserted on the transition
to S5 and then deasserted on the transition to S0;
In down-sequence, SYS_RST_L needs to be asserted on the transition to S5.
This only affects Scarlet.
BUG=b:35647982
BRANCH=none
TEST=minitor SYS_RST_L pin to confirm it is toggled right
Change-Id: Ic73d39c531f9d28b2087a23d58613e98ec80dbd2
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/866115
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
All init hooks complete before tasks are started (since
crrev.com/c/456628), so board_tcpc_init will finish before
the PD tasks start.
Using the init hook instead of CONFIG_USB_PD_TCPC_BOARD_INIT
avoids the problem of board_tcpc_init being called by every
PD task.
BUG=b:72229154
BRANCH=none
TEST=PD still works on grunt,
board_tcpc_init is only called once,
PD task init happens after board_tcpc_init finishes
Change-Id: Ie1263dffce06e9ea2433cc2d08d1537e4a891d40
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/879358
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is used by the keyboard backlight driver. Add support so we can
start talking to this chip.
BUG=b:69379749
BRANCH=none
TEST=i2cscan shows a device at 0x6c on bus 4 now
Change-Id: I951ecd0fa3030f9f408ed0a4504b54950b7ca174
Signed-off-by: Benjamin Gordon <bmgordon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/879081
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This function is no longer used because proto0 boards have been
deprecated. This function is called before I2C is initialized.
This function tries to read board info and causes watchdog to
trigger because timeout is set to zero.
BUG=none
BRANCH=none
TEST=boot Fizz. reboot by 'reboot ap-off'. Observe no watchdog reset.
Change-Id: I3bdebe4fb34dbef552fc89a170efa87d753078c0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/879355
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Host command handler prints every single host command except when
commands are repeated back-to-back. This patch allows each board
decide which commands should be ignored. When debug printf is
suppressed, a global counter is incremented. Developers know there
were commands processed but not reported to the console.
BUG=chromium:803955
BRANCH=none
TEST=Observe 0x97 and 0x98 were not printed. Global suppress
counter is incremented.
Change-Id: I05e8cde9039f602e8fc06c20e89b328e797bd733
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/876952
Reviewed-by: Randall Spangler <rspangler@chromium.org>
After 3 tries, the touchpad is reset by power-cycling it.
BRANCH=none
BUG=b:71688150
TEST=Short SDA/SCL lines, press on touchpad, see that touchpad tasks
retries transaction, and then resets the touchpad power.
TEST=Do ESD discharge, and see that touchpad always recovers.
Change-Id: If0b5eb936d4d2feb3d34a7ec8748869a1b915c34
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/872131
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move enable of TCPC and PPC interrupts from board_init to
board_tcpc_init so they are enabled after the PD tasks have
been initialized.
BUG=b:69378796
BRANCH=none
TEST=PD still works on both ports
Change-Id: Ia6c91e78d95f126b9049994f8f0568ac2e4cec4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/876642
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Grunt HW has these driven from EC to SOC, unlike coral which had
the TCPCs drive the HPD signals to SOC.
BUG=b:71810897
BRANCH=none
TEST=external display works if GPIOs set high on EC console
Change-Id: I40d794cccfdbb46f42642ea1410d75e2281028a1
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/867235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Connect these up so that we can test the hardware.
BUG=b:71902053
BRANCH=none
TEST=manually on EC:
> pwm
PWM channels:
0: 0%
1: 100%
2: 100%
> pwm 1 50
Setting channel 1 to 50
1: 50%
> pwm 2 50
Setting channel 2 to 50
2: 50%
> pwm 1 10
Setting channel 1 to 10
1: 10%
See that the colours changes orange/blue
Change-Id: I9bc3f4c0eb033f58d7bfe524ba99f8dd2e177eef
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/865101
Reviewed-by: Edward Hill <ecgh@chromium.org>
Enabling backlight control module with active low mode enabled.
BUG=b:72007261
BRANCH=none
TEST=Booted grunt board and verified lid sensor toggles backlight
Change-Id: I14a6eec01c4cda6fcb4b821b9a4b6f266b8fe78b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/872234
Reviewed-by: Edward Hill <ecgh@chromium.org>
After VBUS is up, there is a delay of ~500ms for rt946x to determine
'VBUS is ready'.
But we need charger_task to detect AC presence and then set a proper
sleep time immediately.
When using fusb302 to detect VBUS, I almost don't see any delay.
BUG=b:71520398
BRANCH=none
TEST=Confirm BATTERY LED turns on immediately when AC is
plugged in a Scarlet in G3.
Change-Id: If1d6d40081b5822eeb9e012115f8deef172def37
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/869420
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is used by the keyboard backlight driver. Add support for it so we
can use this chip.
BUG=b:69379749
BRANCH=none
TEST=manual:
boot AP
gpioset KB_BL_EN 1
i2cscan
See that bus 5 shows 0x6c now
Change-Id: I37dd497688f7d280119bf2a226e23bee35063e0c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/871135
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This patch adds Cros Board Info APIs. It reads board info from EEPROM.
This patch sets CONFIG_CBI for Fizz to make it use CBI.
BUG=b:70294260
BRANCH=none
TEST=Read data from EEPROM.
Change-Id: I7eb4323188817d46b0450f1d65ac34d1b7e4e220
Reviewed-on: https://chromium-review.googlesource.com/707741
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
ap_state doesn't disable/enable the detect ap interrupt correctly. This
means cr50 is mostly just polling the AP state. Cr50 may not realize the
AP is up until almost a second after it first turned on. This change
reenables the detect ap on interrupt while debouncing the AP state or if
Cr50 thinks the AP is off, so cr50 can more quickly detect the
transition from off to on.
This issue doesn't affect devices that detect the AP with TPM_RST_L,
because we never disable the TPM_RST_L interrupt and that handler calls
ap_on_deferred directly.
BUG=b:71866206
BRANCH=cr50
TEST=run power_state:rec on Dru and make sure there are no tpm irq
timeouts.
Change-Id: I67388f9dce94fb22efe5755a0de563e5af42f8f5
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/869410
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Simple shell to flash the FP MCU firmware from the AP through the STM32
DFU mode (over the SPI interface).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71986991, b:36125319
TEST=run flash_fp_mcu on Meowth and see a new FP MCU is flashed
Change-Id: I99af754b3ed4916ee04a800859f1b28feb640de1
Reviewed-on: https://chromium-review.googlesource.com/866840
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
