We share the same shared memory fields for both batteries. When
the host wants to switch battery to read out:
- The host sets EC_ACPI_MEM_BATTERY_INDEX to the required index
- EC then swaps the data is the shared memory fields, then update
EC_MEMMAP_BATT_INDEX
- Host waits for EC_MEMMAP_BATT_INDEX to have the required value,
then fetches the data
BRANCH=none
BUG=b:65697620
TEST=Boot lux, both /sys/class/power_supply/BAT0 and BAT1 are
present, data is valid.
TEST=Unplug base, BAT1 goes away, replug, BAT1 comes back.
Change-Id: Icce12f9eef2f6f8cde9bae0a968a65e1703d0369
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/888382
Reviewed-by: Gwendal Grignou <gwendal@google.com>
The STM32H7 family has 2 banks of flash (with 2 hardware controllers
able to do 2 parallel operations at the same time).
Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB
variants).
The flash can only be written by 256-bit word (with an additional 10-bit
ECC computed by the hardware).
For the flash write-protection, we cannot use our 'classical' PSTATE
scheme as the erase-blocks are too large (128-kB) to dedicate one to
this and the embedded word in the RO partition would not work as the
flash has ECC and triggers bus-fault when the ECC is incorrect (which
includes the case where the 256-bit word is written a second time).
So we will do the following:
- use the RSS1 bit in the option bytes as the Write-Protect enabled bit.
- if the WP GPIO is set, lock at startup the option bytes until next
reboot.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC
console.
Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6
Reviewed-on: https://chromium-review.googlesource.com/901423
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
We want to build the shmalloc common code in test mode *only* for the
shmalloc test not for all test binaries (which are missing the helper
functions).
The previous version was broken for any board declaring CONFIG_SHMALLOC
(but none were excepted cr50 which has tests disabled)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=emerge-meowth chromeos-ec
Change-Id: Ic89c74569fbadbc75d9090b084adab8f40ddfa5d
Reviewed-on: https://chromium-review.googlesource.com/909210
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This allows hashing or dumping SPI flash from the Cr50 console even on
a locked device, so you can verify the RO Firmware on a system via CCD.
See design doc: go/verify-ro-firmware
(more specifically, "Cr50 console commands for option 1")
BUG=chromium:804507
BRANCH=cr50 release (after testing)
TEST=manual:
# Sample sequence
spihash ap -> requires physical presence; tap power button
spihash 0 1024 -> gives a hash; compare with first 1KB of image.bin
spihash 0 128 dump -> dumps first 128 bytes; compare with image.bin
spihash 128 128 -> offset works
spihash 0 0x100000 -> gives a hash; doesn't watchdog reset
spihdev ec
spihash 0 1024 -> compare with ec.bin
spihash disable
# Test timeout
spihash ap
# Wait 30 seconds
spihash 0 1024 -> still works
# Wait 60 seconds; goes back disabled automatically
spihash 0 1024 -> fails because spihash is disabled
# Presence not required when CCD opened
ccd open
spihash ap -> no PP required
spihash 0 1024 -> works
spihash disable
# Possible for owner to disable via CCD config
ccd -> HashFlash is "Always"
ccd set HashFlash IfOpened
ccd lock
spihash ap -> access denied
# Cleanup
ccd open
ccd reset
ccd lock
Change-Id: I27b5054730dea6b27fbad1b1c4aa0a650e3b4f99
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/889725
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We need to wake up charger task right after AC is plugged
so that the charge state can be updated immediately.
BUG=b:71520398
BRANCH=none
TEST=Confirm charger task wakes up immediately when AC is
plugged in a Scarlet in G3.
Change-Id: I4a65b3da363cdc204b800bd300824dae616770cb
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/869419
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When AP requests cold reboot, currently EC does not perform PMIC
reset because chipset_handle_reboot is executed only after EC jumps
to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME
events because power rails do not cycle.
This patch will make EC execute PMIC reset to before vboot_main.
BUG=b:73093795
BRANCH=none
TEST=reboot, reboot ap-off, verify USB ports are powered after
transitionining to dev mode.
Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/908094
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Prochot/Shutdown Point
a. Prochot on: >=81C, off: <=77C
b. Shutodwn: >=82C
2. custom fan table
There are three projects sharing two tables, and
use Kench & Teemo's table before getting correct OEM ID
because it raises fan speed quicker than the other one.
a. Kench & Teemo & default
b. Sion
BUG=b:70294260
BRANCH=master
TEST=EC can get two fan tables with different cbi value.
Change-Id: Ie1bffbcf5c353a9aae5806f6c2b41554eed22b7d
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/886121
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
BRANCH=none
BUG=b:72722179
TEST=lidopen/lidclose, see that USB interface is getting enabled/disabled
TEST=Close/open sensor with a magnet, see that USB interface is getting
enabled/disabled
TEST=Boot with sensor open, USB interface is on
Change-Id: Ic738fa2f2adea03cd29914bb5fc96a1fa6834122
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/894783
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since there is no KEYPROTO task on chromebox such as fizz and sion, lpc
driver doesn't declare KBC IBF/OBE ISRs for these events. If host put
data in ec's KBC input buffer unexpectedly, exception_panic() will be
executed in default_handler. Then we will see ec print
"=== PROCESS EXCEPTION: 29 ====== xPSR: 01000000 ===" message without
any hard fault and reset.
This CL fixed this symptom by turning off KBC if there is no KEYPROTO task.
We also run suspend stress test on fizz and no watchdog reset symptom
occurred.
BRANCH=none
BUG=b:72353876
TEST=No build errors. Run suspend stress test on fizz and no watchdog
reset occurred.
Change-Id: I4744fac0d6fb2628849c728d4860509434fa2cbb
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/899706
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Fizz has three FETs connected to three registers: PR257, PR258,
PR7824. These control the thresholds of the current monitoring
system.
PR257 PR7824 PR258
For BJ (65W or 90W) off off off
For 4.35A (87W) on off off
For 3.25A (65W) off off on
For 3.00A (60W) off on off
The system power consumption is capped by PR259, which is stuffed
differently depending on the SKU (65W v.s. 90W or U42 v.s. U22).
So, we only need to monitor type-c adapters. For example:
a 90W system powered by 65W type-c charger
b 65W system powered by 60W type-c charger
c 65W system powered by 87W type-c charger
In a case such as (c), we actually do not need to monitor the current
because the max is capped by PR259.
AP is expected to read type-c adapter wattage from EC and control
power consumption to avoid over-current or system browns out.
The current monitoring system doesn't support less than 3A
(e.g. 2.25A, 2.00A). These currents most likely won't be enough to
power the system. However, if they're needed, EC can monitor
PMON_PSYS and trigger H_PROCHOT by itself.
BUG=b:72883633,b:64442692,b:72710630
BRANCH=none
TEST=Boot Fizz on 60W/87W/BJ charger. Verify GPIOs are set as expected.
Change-Id: Ic4c0e599f94b24b5e6c02bbf1998b0b89ecad7bf
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/900491
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
It is not necessary to enable Bank B, as we do not use it.
Also, we have seen a race between enabling the banks and writing
the brightness register to 0xFF, where the chip would reset the
value after it has been set by EC. Adding a short 100us sleep
fixes the issue.
BRANCH=none
BUG=b:69379749
TEST=Flash whiskers, pwm 0 50 works, even after a cold reset.
Change-Id: Ic523a2475c3874c8433eb1b39e927793dd893e8f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/906165
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Benjamin Gordon <bmgordon@chromium.org>
With this change, we can do flashing via flex cable.
BRANCH=none
BUG=b:35573714
TEST=To run "~/trunk/src/platform/ec/util/flash_ec --board=reef_it8320"
and flashing is done and cold reset automatically.
CQ-DEPEND=CL:855978
Change-Id: I078afa6d6f6f8f7bf60a1677e4c357dbe906e7dc
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/344481
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When RMA procedure is completed WP needs to be enabled back.
BRANCH=cr50, cr50-mp
BUG=b:37952913, b:73075443
TEST=on a Robo device, verified that WP is enabled, took the device
through RMA unlock, verified that WP is disabled, took the device
through RMA disable, verified that WP is enabled again.
Also confirmed that after RMA is disabled WP status follows the
battery.
Change-Id: Iad6af7d16aadcd10d580f709aeb942cf508a8489
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/905926
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The TPM task is running on a higher priority than the hook task
invoking TPM reset for RMA purposes. The waiting task ID value needs
to be set before TPM task is signaled to reset.
BRANCH=cr50, cr50-mp
BUG=b:37952913
TEST=with the corresponding ccd_config.c changes fully verified RMA
process (not just generating and processing the challenge).
Change-Id: Id112d59ae0c3fd31a32e652c6a043fc3fd3bbe07
Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/905925
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Indentation in charger_task is getting out of control, let's move
the logic to a new function.
BRANCH=none
BUG=b:71881017
TEST=Flash lux and wand, battery algorithm works as expected.
Change-Id: Ife008370218f0d9eb0f96088ec144b0aba40716f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/901442
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
On dual battery systems, this allows to keep both batteries
information in similar structures. This also means that battery
information can only be fetched via host commands
EC_CMD_BATTERY_GET_STATIC/DYNAMIC (next CL will make it possible
to fetch the information via shared memory/ACPI).
BRANCH=none
BUG=b:65697620
TEST=Boot lux/wand, dual-battery algorithm works, AP can fetch
both battery information via host commands.
Change-Id: I3c087e8f378c5cef0006f6bfe58335228a880e5b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/888381
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit adds support for a common framework for PWM controlled LEDs.
If there are multiple LEDs, they will all follow the same pattern. The
pattern is such that it follows the Chrome OS LED behaviour
specification, essentially a similar version of led_policy_std.c but for
PWM controlled LEDs.
To use this framework, a board must do the following:
- First, define the number of logical PWM LEDs which will be controlled
by this common policy, CONFIG_LED_PWM_COUNT.
- Then declare those logical LEDs and define the PWM channels that
comprise those LEDs. (struct pwm_led pwm_leds[]).
- Next, define what each color should look like (struct pwm_led
led_color_map[]).
By default, the colors follow the recommended colors in the LED
behaviour spec, which assume an LED with a red and green channel. If a
board differs or wishes to change the colors in general, they can
redefine the colors (CONFIG_LED_PWM_*_COLOR) as they see fit. The
colors must be one in enum ec_led_colors. These colors are the ones
that can represent the charging state, SoC state, etc.
BUG=b:69138917,chromium:752553
BRANCH=None
TEST=make -j buildall
TEST=Enable led_pwm for meowth, and verify that LEDs behave as expected.
Change-Id: I945b86a7f8ed30df58d7da835d83577192548bea
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/888220
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
GCC 6.3 can't tell that we enforce the variable 'size' being set,
so initialize it to 0 to make the warning go away. The code does
actually verify that size is set, but not by checking the size
variable itself.
util/cbi-util.c: In function 'main':
util/cbi-util.c:139:8: error: 'size' may be used uninitialized in this
function [-Werror=maybe-uninitialized]
buf = malloc(size);
^~~~~~~~~~~~
util/cbi-util.c:233:11: note: 'size' was declared here
uint32_t size;
^~~~
BUG=b:72609872
BRANCH=None
TEST=Build with coreboot toolchain.
Change-Id: Ide41a0fce40254f2fa3a8626dec75840a728d967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/890703
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
The HPD pins for meowth and zoombini go from the EC to the AP. This
commit drives the HPD correctly.
BUG=b:72413020
BRANCH=None
TEST=Flash meowth; Use a couple charge-through hubs, unplug HDMI cable,
replug, verify AP sees new DP sink.
Change-Id: Ie1f86378c59fc4a717edc537ff8afe01b21d9b68
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/888226
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
touchpad can be powered off when the USB interface is disabled
without setting the remote wake feature
(USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be ignored
anyway.
BRANCH=none
BUG=b:72683995
TEST=touchpad is disabled when lid is closed.
Change-Id: I688fce16ab8c75330e588ec130fb2aa499fc0ed1
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/897069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Keyboard matrix scanning can be disabled when the USB interface is
disabled without setting the remote wake feature
(USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be
ignored anyway.
BRANCH=none
BUG=b:72683995
TEST=keyboard matrix scanning is disabled when lid is closed.
Change-Id: I0b2346cc3426b9ef51127424f9953fd5c20ecd49
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/897068
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch makes EC enable PD communication if it's running in
manual recovery mode. This is required to show recovery screen
on a type-c monitor.
This patch also makes EC-EFS ignore power availability. It will
make EC verify & jump to RW even if power is sourced by a barrel
jack adapter. This should allow depthcharge to show screens
(e.g. broken, warning) on a type-c monitor.
BUG=b:72387533
BRANCH=none
TEST=On Fizz with type-c monitor, verify
- Recovery screen is displayed in manual recovery mode.
- Critical update screen is displayed in normal mode.
- Warning screen is displayed in developer mode.
Monitors tested: Dingdong, Dell S2718D
Change-Id: Ib53e02d1e5c0f5b2d96d9a02fd33022f92e52b04
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/898346
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Host command handler prints every single host command except when
commands are repeated back-to-back. Some commands do not provide
useful info when studying feedback reports or what is worse they
may hide critical info by flooding the EC log.
BUG=chromium:803955
BRANCH=none
TEST=Observe 'HC 0x115' is not printed.
Change-Id: I4901b27bbfedd54dc0d364b16c49d4ed0dea0fc4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/896694
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Because H1 monitor tx/rx signals to detect servo board,
so we can't pull-up tx/rx or the DETECT_SERVO of H1 will
be always high even the servo board isn't connected.
BUG=none
BRANCH=none
TEST=H1 detect servo board correctly.
Change-Id: I2f2dfa220ed77478e6e622a0ed1189f559044aa3
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/897315
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To avoid issues where adapter would drive against OTG of lid or
base, and to make sure that we do not over-current the adapter,
we disconnect the base/lid power transfer whenever a new
adapter is connected.
We reenable power transfer as needed.
We also separate out base current control as a new function,
that allows us to record the previous base current only when
the base charge control command is successful, and ignore
errors until the base is responsive for the first time.
Finally, we make sure that
charge_allocate_input_current_limit is only called from a
single location in charger_task.
BRANCH=none
BUG=b:71881017
TEST=Plug/unplug base, reset lux EC, connect charger.
Base is detected, power allocation works as expected.
Change-Id: I8b206d5b0fbcf0fe868b56a0336745aebe2a6dc2
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/880021
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This change creates a state machine to handle ap uart detection. It
removes all of the ap_uart stuff from ap_state.c and moves it to
ap_uart_state.c. All boards will now use ap_uart to enable/disable ap
uart and tpm_rst_l to detect the ap state.
Separate ap uart detection from ap detection, so we can disable the ap
uart without enabling deep sleep. If the ap is in S3 on ARM devices,
Cr50 wont be in deep sleep, but the AP UART RX signal wont be pulled up.
In this case we need cr50 ap rx to be disabled and deep sleep to be
disabled.
BUG=b:35647982
BRANCH=cr50
TEST=run firmware_Cr50DeviceState on scalet and electro
Change-Id: I81336a9e232df8d44b325eef59327a1c06a80cba
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/884307
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
If during PMIC initialization, it is identified that there was a VR
fault, then dump fault registers 0x16 and 0x17 to EC console. This
information is very useful during debugging sudden power losses in
field and so it is printed out to EC console.
Additionally, add panic reason with these register values as panic
data so that OS can provide this information in cros ec
panicinfo. This helps in retaining the information even if EC console
logs overflow.
BUG=b:65026806
BRANCH=eve
TEST=Verified that on a VCCIO shutdown, PMIC VR fault is
reported: "PMIC VRFAULT: PWRSTAT1=0x80 PWRSTAT2=0x00"
Change-Id: I583e513f865aeefc7dfc9860ce0ce9789808dea2
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/896163
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In particular, this will allow touchpad driver and keyboard matrix
scanning to be powered off/disabled when the USB interface is
disabled without setting the remote wake feature
(USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be
ignored anyway.
BRANCH=none
BUG=b:72683995
TEST=With next CLs, touchpad and keyboard matrix scanning are disabled
when lid is closed.
Change-Id: I3750bfaf8c31cde075adf9da4fef39753b8981c5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/897067
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change the EC to drive the Hotplug Detect (HPD) GPIOs.
Grunt HW has these driven from EC to SOC, unlike coral which had
the TCPCs drive the HPD signals to SOC.
BUG=b:71810897
BRANCH=none
TEST=external display works using USB-C to DP adapter on both ports
Change-Id: I22ec9eecc5bdf9c6463dd3ce208d051faf15c57a
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/892099
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This patch makes EC_CMD_SET_CROS_BOARD_INFO return
EC_RES_ACCESS_DENIED if the command fails due to write-protect
switch.
BUG=b:70294260
BRANCH=none
TEST=Verify 'ectool cbi set 2 4' prints 'WP enabled?' when WP
is enabled.
Change-Id: I7c27ee748caf32e57f22ab79edcbff96e42c44ad
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/897683
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Automated code scanner highlighted a few problems in the recent ode
additions. This patch fixes the problems.
BRANCH=cr50
BUG=none
TEST=none
Change-Id: I1f199eb5d2af992384ab04f3010b4b646464a70f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/897993
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
