This change removes the uart disable in rdd_disconnect. It used to be
necessary because we used to disable device state detection in
rdd_disconnect. Without device state detect we had to disable the AP and
EC uart to make sure there were no interrupt storms. Now we keep device
state detection running all the time. It handles enabling/disabling the
AP and EC uart when it senses the RX signals aren't pulled up.
UART is only enabled/disabled when cr50 detects that the AP or EC state
changed from off to on or on to off. If the debug cable is detached and
then reattched the uart will be disabled on detach, but it won't be
reenabled until the AP/EC are rebooted.
BUG=chrome-os-partner:58222
BRANCH=none
TEST=Detach and reattach suzyq without rebooting the AP or EC and make
sure both consoles come back after reattaching the cable.
Change-Id: Id104e12dc533e8d7047f32aebd41abd1c959d267
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410269
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enable fast charging profile config (CONFIG_CHARGER_PROFILE_OVERRIDE)
so that the battery desired current & voltage can be selected for given
rated performance values.
BUG=chrome-os-partner:59779
BRANCH=none
TEST=Manually overrode the temperature and voltage. Observed correct
charge profile config is selected for each tests.
Change-Id: I080a3ace6d2f77bb6b97911b7705a44ec563258b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410824
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
PD alternate mode is covered in tcpc interface. So tcpci_tcpm_init()
doesn't reset HPD. If keeping HDMI/DP type-C cable connected, doing
sysjump sets HPD signal to high while it's already high(this high comes
from previous state), then OS doesn't output to HDMI/DP monitor.
BUG=None
BRANCH=none
TEST=make buildall
Change-Id: Ic3bc75b1e5579816d8c1b294fe2eb65a20e3eae3
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/409751
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added battery charging profile settings as given in the datasheet.
BUG=chrome-os-partner:58553
BRANCH=none
TEST=Manually verified on reef. VBAT is equal to battery voltage.
Previous/current Charge status is equal to the conditions given
in the datasheet.
Change-Id: Ie04619a122fe52d6768c03ff5156b368e3f2d340
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/398080
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This changes the usb descriptor to set the MaxPower to 0mA instead of
500mA.
BUG=chrome-os-partner:59564
BRANCH=none
TEST=Verify 'lsusb -vd 18d1:5014 | grep MaxPower' shows the power is 0mA
Change-Id: Ieeb8dec6c205f4fe51392f8106b3a0ed7d3ea0a5
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410288
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
This allows custom TPM commands to be declared using the a
DECLARE_VENDOR_COMMAND macro instead of the original (and still
unchanged) DECLARE_EXTENSION_COMMAND macro.
The new commands are nearly identical, but they are encapsulated
using the vendor-specific protocols described in the TPMv2 spec.
Our original extensions use a non-standard command code, and
return a non-standard struct on completion, which can be
confusing to standard TPM drivers and tools.
Demonstrating the use of the new macros, this adds commands to
obtain the state of the Cr50 restricted console lock, or to set
the lock. There is intentionally no command to unlock the
console.
Note that this CL just adds the commands to the Cr50. We still
need to provide a nice userspace utility for the AP to use.
BUG=chrome-os-partner:58230
BUG=chrome-os-partner:57940
BRANCH=none
TEST=make buildall; load, boot, test, and update again on Reef
On Reef, I can use the trunks_send tool to send the raw TPM bytes
to invoke these commands:
Get the lock state:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000D00000000001000
The last byte 00 indicates that the lock is NOT set, so set it:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000C000000000011
Success. On the Cr50 console, I see it take effect:
[480.080444 The console is locked]
Query the state again:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000D00000000001001
and now the last byte 01 indicates that the console is locked.
And of course the existing extension commands still work as
before. In addition to uploading firmware, I can use the
usb_updater from my build machine to query the running firmware
version:
$ ./extra/usb_updater/usb_updater -f
open_device 18d1:5014
found interface 4 endpoint 5, chunk_len 64
READY
-------
start
Target running protocol version 5
Offsets: backup RO at 0x40000, backup RW at 0x4000
Keyids: RO 0x3716ee6b, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.9
$
Change-Id: I7fb1d888bf808c2ef0b2b07c782e926063cc2cc4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409692
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890
BRANCH=none
TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption
Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/399882
Reviewed-by: David Hendricks <dhendrix@chromium.org>
If PS8751 goes into low power mode during sysjump, then tcpm_init will
fail since PS8751 is not accessible via I2C, so force it to wake up
during hook_init.
BUG=chrome-os-partner:59693
BRANCH=none
TEST=Verified PS8751 port on reef is functional after sysjump.
Change-Id: I2aa5a80b2ea9c17a01e4cba04493f83cb0a39955
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410132
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Various cryptographic operations leak timing
information if comparisons are not executed
in constant time. This change adds DCRYPTO_equals(),
a constant runtime comparator.
Also replace crypto related callsites that used
memcmp() as a binary comparator.
BUG=none
BRANCH=none
TEST=tcg tests pass
Change-Id: I3d3da3c0524c3a349d60675902d1f2d338ad455f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/410163
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The firmware provision job running in the lab calls the flash_ec
script with the --chip parameter, instead of the --board parameter.
So only check if the board name is in the raiden list if it is a
non-empty board.
BRANCH=none
BUG=chrome-os-partner:58039
TEST=Manually triggered the flash_ec command:
$ flash_ec --chip=npcx_spi --image=${IMAGE} --port=9999 --raiden
Change-Id: I25fef906d93803a94c544f7699ce494a84c46bd8
Reviewed-on: https://chromium-review.googlesource.com/410162
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CTS task wakes up A and C then goes to sleep:
CTS -> A, C -> A -> B -> C
Since C has a higher priority, C should run first. This should result
in C running one more time than A (or B).
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: I89c733ba3aab09b293edf8583d6ed73791531e59
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409535
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Task A wakes up B and goes to sleep. Task B wakes up C then goes to
sleep. Task C wakes up A then goes to sleep. This is repeated
repeat_count times:
A -> B -> C -> A -> ...
It's expected all tasks to run exactly repeat_count times. Tick task
runs to inject some irregularity.
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: Ib7227f05f09b7a49f8528aff6e6e8d3e6df93ba7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409534
Reviewed-by: Randall Spangler <rspangler@chromium.org>
These keys are much quicker to verify (259ms to 51ms on a -M0 at
48 Mhz), so they can be used when timing is critical and
verification needs to be performed on the board.
BRANCH=none
BUG=chromium:663631
TEST=make buildall -j && make run-rsa
TEST=make run-rsa3 (next commit)
Change-Id: I0da4b3e21543bb6f7b18e8b6ddc5e153046a61b8
Reviewed-on: https://chromium-review.googlesource.com/408006
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When bus obfuscation is enabled we have the chance of doing a security
reset when resuming from sleep. Since we cannot disable bus obfuscation
on current boards, we need to disable sleep.
BUG=chrome-os-partner:57994
BRANCH=none
TEST=make buildall
Change-Id: I6f49278a9b41c1d15c646838044e34f03b979479
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409576
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When kernel get EC_HOST_EVENT_PD_MCU event and query power state, we may
not done refresh here. Delay EC_HOST_EVENT_PD_MCU event to avoid this
race.
BUG=chrome-os-partner:59499
BRANCH=gru
TEST=Manual on kevin, check power state correct after unplug charger
Change-Id: Ib88acf5a39c2780c6e40144ccebfba17cf84f77c
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/408131
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a nested interrupt test to eCTS. Higher priority IRQ is fired,
followed by lower priority IRQ. Handlers should be executed
sequentially.
P1 *-----*
/ \
P2 / *-----*
/ \
task_cts ----* *----
B C A D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m interrupt; make buildall
Change-Id: Ia9f1bf4205cefe8bdc11cc0aa3ad2057359b73ef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409611
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a nested interrupt test to eCTS. Lower priority IRQ is fired,
followed by higher priority IRQ. Handler executions should be nested.
P1 *-----*
/ \
P2 *----* *----*
/ \
task_cts ----* *----
A B C D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer; make buildall
Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f
Reviewed-on: https://chromium-review.googlesource.com/408797
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
After a board is reset for setting up a tty port, the host should
wait for a few seconds before flushing the port as the board may
still be booting. This should prevent output from the previous boot
from creeping into a test run.
BUG=none
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer
Change-Id: I1fb567a3a8ddcfff61865b6db3866c56be386c4a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/408759
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If our 32-bit usec timer is close to overflow, we may deep sleep several
times in succession without making any adjustment to our count, causing
deadlines on the other side (eg. HOOK_TICK expiration) to be reached much
slower than expected. Avoid this by not entering deep sleep if our timer
is about to overflow. This will result in a <= HOOK_TICK_INTERVAL (200ms
interval) period of not entering deep sleep, every ~4300 seconds.
BUG=chrome-os-partner:59240
BRANCH=gru
TEST=Verify 3x kevin units survive 16 hours in S3 without EC watchdog.
Change-Id: I2126458be8820f78212e19c2bb79242ff1194f6f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409673
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Wait for ITEN bit to be set / cleared, since writing this bit just
sets a 'request'.
- Ensure ITIM_EVENT_NO reg is set with minimum value 1, per the
datasheet.
- Don't dsleep if our wake event is in the past (eg. wake event will
occur any time now)
BUG=chrome-os-partner:59240
BRANCH=gru
TEST=Manual on kevin, verify that dsleep period never exceeds expected
wait period. Also verify that EC watchdog doesn't occur after 5 hours in
S3.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iedb2723c3f12b74dea66082b1d8b8ce1b6e7d945
Reviewed-on: https://chromium-review.googlesource.com/409672
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Since we are out of host event bits, add a bit to indicate extended host
event exists. This is put in as a placeholder for now so that we don't
lose out the last available hostevent bit.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully
Change-Id: If35a246f3da511fde9f8c0bba419afb76a1a9827
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407804
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds new key combination (Left_Shift+Esc+Refresh+Power) that triggers
recovery mode by setting a new host event
EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT. This host event can be used
whenever user wants to request entry into recovery mode by
reinitializing all the hardware state (e.g. memory retraining).
BUG=chrome-os-partner:56643,chrome-os-partner:59352
BRANCH=None
TEST=Verified that device retrains memory in recovery mode
with (Left_Shift+Esc+Refresh+Power) on reef.
Change-Id: I2e08997acfd9e22270b8ce7a5b589cd5630645f8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407827
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Simple API to set/get the tablet mode. It can be set via lid angle
calculation or if a board has a dedicated HAL sensor/GPIO.
Merged from glados branch, add MKBP switch support.
BUG=chromium:606718
BRANCH=gru
TEST=Check with Cave that both mode works.
Reviewed-on: https://chromium-review.googlesource.com/402089
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e)
Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404915
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We were getting occasional stack overflow and watchdog timeouts
when clearing NVMEM. Bump up the stack size a bit in the HOOKS
task, and pet the watchdog before invoking the tpm2 init
functions.
BUG=chrome-os-partner:59419
BRANCH=none
TEST=make buildall, manual
Lock the console, then unlock it. This will reboot the EC & AP,
but should never reboot the Cr50.
Before this CL, it did about half the time.
After, it doesn't.
Change-Id: I33adfeb7360bf7d146a55ef16c923a1a0416393d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407847
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When attaching a dump (not PD protocol) TypeC charger, the incorrect
charger type was being selected and therefore it was not enabling 3A
charging. I tracked this issue down to the anx74xx_tcpm_get_cc()
function returning a incorrect value. The expected value was
TYPEC_CC_VOLT_SNK_3_0, but instead it was returning
TYPEC_CC_VOLT_SNK_DEF.
The reason the incorrect cc type was being returned is because the if,
else if, construct didn't work properly for the 3A case where the
upper 2 bits are set. Modified this routine to use a case statement
and consolidated the checks for both cc1 and cc2 into one helper
function.
BRANCH=none
BUG=chrome-os-partner:58738
TEST=manual
Connected zinger and guppy chargers and verified correct cc type was
being returned. In addition tested hoho/dingdong adapters as well as
suzyq. Tested both cable orientations to verify that cc1 and cc2
returned the correct values.
With guppy connected, now see this output on ec console:
C0 HARD RST TX
C0 st5
C0 st36
C0 st37
C0 HARD RST TX
C0 st5
[1921.980074 AC on]
[1922.008140 charge_request(8688mV, 9280mA)]
C0 st6
[1922.910539 Ramp p0 st5 3000mA 3000mA]
Change-Id: I8b31c7ce366f383dfcc2f6e850b76a83340a02a1
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406642
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Since PD task are highest priority, the 50msec delay between was intended
allow other tasks to execute if PD has continuous interrupt. With two
separate TCPC handled by host_command_pd task, interrupt from one TCPC will
block the interrupt handling of another TCPC by this 50msec and cause
error in the PD negotiation.
Reduced to 5msec to ensure TCPC interrupt is handled as soon as possible
while allow other tasks to execute if needed.
BUG=chrome-os-partner:59061
BRANCH=none
TEST=Verify zinger can negotiate to 20V, hoho can get display. Also tested
with faking PD interrupt always asserted to check for watchdog reset.
Change-Id: I9b71277a3d65923f1f5bbfd744b3399e34fd0e6c
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/407542
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This change is a safegaurd to ensure that TPM register data is always
placed in the correct location in the HW read I2CS fifo. It is only
checked for 1 or 4 byte regsiter reads. Because of the way in which a
TPM command is sent and the response is read, there are multiple reads
of the STS register prior to reading the TPM fifo register. Therefore
ensuring the fifo has zero depth when 1 or 4 byte regsiter reads,
improves the robustness of the design.
Added a counter to track the number of times the fifo is adjusted and
a new console command 'i2cs disp|rst' to display the count and reset
it to 0 if desired.
Removed section in code for TPM fifo register reads intended to handle
the case where there was a mismatch between how many bytes were copied
into the fifo and the number read by the host. Since the burstcount
field in the status register always contains a valid amount of data
that can be read by the host, there should not be cases where the
host reads less data than was copied from the TPM fifo register. In
the unexpected cases where the host may not drain all of the I2CS read
fifo data during a TPM register read, the I2CS fifo depth will be
corrected the next time that it reads either the access or STS
register which happens prior to the start of any TPM transaction.
BRANCH=none
BUG=chrome-os-partner:57338,chrome-os-partner:59191
TEST=manual
Booted Reef and verfied that TPM functionality is working.
Change-Id: I065a55e64bbcc0cb3357a2bd83447a05400b8899
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382689
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The jittery clock and trng security features require high permissions to
be initialized. In the future these initializations and the permission
level drop may be moved to RO.
This change adds permission level checks before trying to access any
registers that require high permission, so when we update RO to change
the permission RW can still function fine.
BUG=chrome-os-partner:59107
BRANCH=none
TEST=Move the permission drop to the beginning of main and verify the
system still boots.
Change-Id: I5b7cb856decd0640288ad3476f875ec9edc42635
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405840
Don't queue non-wake events, and ensure wake events (and all subsequent
events) always get queued.
BUG=chrome-os-partner:59248, chrome-os-partner:59336
BRANCH=gru
TEST=Manual on kevin, go to suspend, press volume keys dozens of times,
press 'shift', verify device wakes. Place cursor on URL bar, go to
suspend, type "google" quickly, verify device wakes and "google" appears
on URL bar. Go to suspend, press 'VolUp' key 5 times, press keyboard,
verify device wakes and no volume meter is seen on display.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibe761187fbcefd686776a512786550970a6fc067
Reviewed-on: https://chromium-review.googlesource.com/405717
Commit-Queue: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(cherry picked from commit aa2f01566314604404e104d7975c6c755c22a601)
Reviewed-on: https://chromium-review.googlesource.com/407958
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
