include/config_std_internal_flash.h is an optional header that
can be used to implement the most common EC flash layout.
However, CONFIG_INTERNAL_STORAGE, CONFIG_MAPPED_STORAGE, and
CONFIG_MAPPED_STORAGE_BASE are fixed by the SoC, so they belong
in config_chip.h, not in the optional header.
BRANCH=none
BUG=chrome-os-partner:23796
TEST=make buildall
Refactoring only, no behavioral differences.
Change-Id: I114c3e194837041920e6f228a2bed6747be8231c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301330
Reviewed-by: Shawn N <shawnn@chromium.org>
Returns the most significant bit set.
Replace 31 - __builtin_clz(x), so x must be different from 0.
Use get_next_bit when not on the performance path,
on performance path set the bit field just after reading it.
BRANCH=smaug
BUG=none
TEST=compile, check Ryu still works.
Change-Id: Ie1a4cda4188f45b4bf92d0549d5c8fb401a30e5d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301300
The current largest task size is not big enough,
we get stack overflow after one or several calibration requests.
BRANCH=smaug
BUG=chrome-os-partner:45570
TEST=After the change a loop of calibrate does not crash the EC.
Change-Id: I9681a890eddf274ab496e8ca6249c7ebca5edab5
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/301215
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Host access to the PNPCFG registers is disabled.
2. UART2 for host if necessary.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. host can't access the PNPCFG registers.
2. out I/O port 0x2f8 '0x30, 0x31, 0x32, 0x33, and 0x34'
will have console message '01234'.
Change-Id: If07bdc129105f5248661d929e6858d4063c452ee
Reviewed-on: https://chromium-review.googlesource.com/300266
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The previous commits left npcx in a bad state. Change
CONFIG_PROGRAM_MEMORY_BASE to point to the actual start of code memory
and correct the linker file.
This still results in a non-working npcx image (more changes
forthcoming) but it does build.
BUG=chrome-os-partner:23796
TEST=make clean; make buildall -j
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia300c5d18695dccd8d9fd9a6122cd7d30353adfa
Reviewed-on: https://chromium-review.googlesource.com/300295
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. Fix fan turns on during sysjump if fan is disabled.
2. Remove unused board function.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1-1. Console 'sysjump RW' and fan keeps off.
1-2. Console 'fanset 4000' or 'fanset 0' and 'sysjump',
it dose maintain the fan RPM.
Change-Id: I531d49c2a8a9fea68af4507339c7be97367c504c
Reviewed-on: https://chromium-review.googlesource.com/299650
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. add lpc_keyboard_clear_buffer() function.
2. Enable P80L function, that LPC I/O port 80h data can be mapped
to BRAM bank1 (offset 0x80 ~ 0xBF).
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. The lpc_keyboard_clear_buffer() function can clear OBF.
2. 80h port, console command port80.
3. 62h/66h port.
3-a. out 66h 80h, out 62h 00h, in 62h 02h
3-b. out 66h 81h, out 62h 01h, out 62h 55h
3-c. out 66h 80h, out 62h 01h, in 62h 55h
3-d. out 66h 80h, out 62h 02h, in 62h aah
4. Host command "version".
Change-Id: Id2b5a5813cbe8edfc4ecc7b153874b819d460f43
Reviewed-on: https://chromium-review.googlesource.com/298421
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Instead of mocking i2c_read8/16/32, mock i2c_xfer.
We can now test code that call i2c_xfer directly and
test common/i2c.c
BRANCH=samus, ryu
BUG=chrome-os-partner:45223
TEST=Unit tests pass.
Change-Id: Iaa772515c40cf55d2050d0019e2062d63278adc0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/299768
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Since there is no more concept of a flash region belonging only to the
EC, we only need one FLASH_SIZE config, which represents the actual
physical size of flash.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6
Reviewed-on: https://chromium-review.googlesource.com/297824
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support architectures with non-contiguous writable and
protected regions, change storage offsets to be relative to writable and
protected regions, rather than relative to "the start of the region of
storage belonging to the EC".
Spec doc available at https://goo.gl/fnzTvr.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4
Reviewed-on: https://chromium-review.googlesource.com/297823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since the STM32 flash write protection was re-factored between STM32F0
and STM32F/F3, the common STM32 flash code checks whether the chip needs
a reboot to synchronize its write protection state (as this can be done
only with an OBL_LAUNCH triggered reset on STM32F0)
but for platforms able to set immediatly the full write-protection
(STM32F/STM32F3 with Cortex-M3 core using the bus fault interception
code) where there is no EC_FLASH_PROTECT_ALL_AT_BOOT flag, this might
trigger a reset loop in the RO code when the flash is write-protected.
Make the check conditional to the existence of EC_FLASH_PROTECT_ALL_AT_BOOT.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:45288
TEST=On a smaug board with hardware write protect enable,
enable software write protect from the AP command line:
flashrom -p ec --wp-range 0 0x20000
flashrom -p ec --wp-enable
ectool reboot_ec RO
reboot -p
then, go to fastboot mode :
adb reboot-bootloader
and see the machine booting properly.
Change-Id: I93f78cb8e9e918c8efe374bd757b79bc87243e2c
Reviewed-on: https://chromium-review.googlesource.com/299555
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 39a0feb45b0c14ea5eb008329f2b8ea7a9b17c8a)
Reviewed-on: https://chromium-review.googlesource.com/299762
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Initialise the ALTERNATE GPIO level flags along with rest of the flags
to prevent GPIO toggling during I2C initialization.
BUG=chrome-os-partner:44821
BRANCH=none
TEST=Manually tested on Kunimitsu FAB3.
I2C SDA & SCL lines do not toggle during I2C initialization.
Soon after the I2C init is done, read/write to PMIC is success.
Change-Id: I70f728017b00f407a0422fd4aa4dbfd8590d74de
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/298242
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Keep the state of reserved bits in SLP_EN registers when sleeping and
waking from sleep.
BUG=chrome-os-partner:45003
TEST=Manual on glados. Go to S3 and measure EC power. Go to deep sleep
and wake. Re-measure power and verify that it is not ~60% higher than
originally measured.
BRANCH=Strago
Change-Id: I6b6b0efcd146fe1a68b41b9b33b25740090dc08f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/298655
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When system timer stops while in heavysleep idle task,
hibernation timer maintains system time and system timer's
recovery is done with reading from hibernation timer.
If hibernation timer setting/reading is incorrect, system timer
recovery is incorrect and evenytually this will result in
quicker/more frequent task scheduling and eventually faster
sleep LED blinking at S3 and higher S3 power consumption.
BRANCH=firmware-strago-7287.B
BUG=chrome-os-partner:37576
TEST=1. measure S3 LED blinking time(probing GPIO pin with scope
2. For debug purpose, let system timer keeps running and compare
internval from system timer reading (t1 - t0) and one from
hibernation timer.
Change-Id: Iace3d29c9e20c0ea863c25eacb69d50858e204b7
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/297753
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 86e7e64e3b5d27a80e1fac296776c0e2fb57912d)
Reviewed-on: https://chromium-review.googlesource.com/297796
Commit-Ready: Divya Jyothi <divya.jyothi@intel.com>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
When a debug accessory is connected to the type-C port while the write
protection is enabled, put the case closed debugging in "partial" mode
rather than "full".
Update the "partial" mode to provide read-only access to the AP and EC
consoles.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:44700
TEST=check the EC console input/output over USB is still working with SuzyQ
on a write-protected system, verify that the console input is disabled.
Change-Id: I5baa03d6e738d06437c45469f46b286e76a755a4
Reviewed-on: https://chromium-review.googlesource.com/297141
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Since the length of flash-write function used by host command is not
aligned to 256 bytes, we need to split it into several sequences to make sure
it won't exceed page buffer size of flash.
Add i2c stop condition checking to avoid unnecessary i2c unwedge operations.
We found some battery will held scl for a while and master cann't issue stop
condition immediately.
Modified drivers:
1. flash.c: Add support for sequence programing.
2. i2c.c: Add i2c stop condition checking mechanism.
3. i2c.c: Fixed bug of i2c_is_raw_mode. (wrong bit offset)
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I4f35a617466ba37bcc4e3aa5324c8950f824a4c2
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/295662
Commit-Ready: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Floating point is used in very few places in the code, none of which are
needed by mec1322 boards (yet). If needed, individual boards can define
CONFIG_FPU.
BUG=None
TEST=Verify glados continues to boot AP successfully and image is shrunk
by 64 bytes.
BRANCH=Strago
Change-Id: I6ea46c15bedbc498e7baa96098b002d711ac20fb
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297029
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Based on feedback from programmers, it's not clear when
config_std_internal_flash should be used, and when non-standard
chip-specific layouts need to be defined. Add clarity here with the
following changes:
- Explain in-depth the one config that config_std_internal_flash should
be used for.
- Move non-standard chip-level flash layout CONFIGs to their own new
chip-level file, config_flash_layout. All chips should either include
config_std_internal_flash.h OR define their own layout in their own
config_flash_layout.
Functionally, this change is a NOP.
BUG=chrome-os-partner:23796
TEST=`make buildall -j`
BRANCH=None
Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296527
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Certain boards may need to handle fixing up the RESET_FLAG_s
because of the boards' designs. Provide an optional per-chip
implementation to save the reset flags. Note that this
function is not protected by a CONFIG_ option as it can just
be implemented by the chip if a board requires it. Lastly,
implement chip_save_reset_flags() for mec1322 for future use.
BUG=chrome-os-partner:44527
BRANCH=None
TEST=Built and booted on glados.
Change-Id: I604fe4e6a069f31727bab52288595a349e3dbe72
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295115
Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The console support in lfw was not very in for printing messages.
The version was smashed against the name of the program and
the image type was at the same column as end of version:
littlefwglados_1.1.9999-f3a5046
lfw-RO load
Fix this by adding a space after the program name and outputting
a carriage return if a new line is encountered. With these changes
the new console looks like:
littlefw glados_1.1.9999-f3a5046
lfw-RO load
BUG=chrome-os-partner:44527
BRANCH=None
TEST=Built for glados. 'reboot' shows legible console output.
Change-Id: I7b80b2c7db453c09a401a740155de98e78f3cf84
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295112
Reviewed-by: Shawn N <shawnn@chromium.org>
If clk or dat aren't pulled up for an extended period, the i2c
controller may get into a wedged state that requires a controller reset
to recover from. There are no outward signs of the controller being in
such a state, other than transaction timeouts. Therefore, on a
transaction timeout, reset the controller.
BUG=chrome-os-partner:43270
TEST=Manual on glados:
- Run `gpioset PP3300_USB_PD_EN 0` on PD console and wait several seconds
- Run `gpioset PP3300_USB_PD_EN 1` on PD console
- Run `i2cscan` and verify all ports / devices ack
- Repeat above several times
BRANCH=None
Change-Id: I2ae42762ee6c961224ff50309a448475b67854b5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295404
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The signer utility needs to be built and the flat image needs to be
signed. The signer utility is written in C++, supporting this required
adding a new make command to Makefile.rules and a build file for the
utility.
The signing now needs to be a part of generating the .flat file. To
achieve this an alternative set of rules is defined in Makfile.rules
for targets where RO image needs to be signed.
Rules for converting elf to hex have been consolidated as there is no
need to omit the --set-section-flags when it does not apply.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=as follows:
- ran 'rm build/cr50; make BOARD=cr50'
- observed that both build/cr50/ec.bin and
build/cr50/RO/ec.RO.flat have the required signature header in
the first 1024 bytes.
- verified that the cr50 board can be booted over SPI using the
image in build/cr50/RO/ec.RO.flat
Change-Id: Iacc22561de67fadfaf8e049bf9578cbd08cfad86
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295291
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This changes the register description to match the newer FPGA version.
The new version supports firmware integrity verification as well as
bootstrapping over SPI slave interface.
BRANCH=none
BUG=chrome-os-partner:43791
TEST=with the rest of the patches (providing ability to sign firmware
and load it over SPI) the code gets signed properly and loaded
and started on the target
Change-Id: Ibebe5f6c510fbfb2c7c6ff40ab58ea643f051b1b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295211
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Leave 1024 bytes at the cr50 RO section for the signature required by
maskrom bootloader.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with this and other changes the latest cr50 image gets signed and
booted properly.
Change-Id: I64efe242b958bbb4e320cb3bb16c653d210dd662
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295201
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This DMA receiver uses a separate small circular buffer to DMA into.
This allows the DMA transaction to be made circular, and thus it does
not require the interrupt latency to be low enough to setup the next
transfer before the next character comes in.
Additional diagnostics output have been added to the usart_info console
command to facilitate tuning of the FIFO size.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify DMA works by cross connecting two discovery boards
Change-Id: Idcdf95a47fadf21ec2154f0c9128cd3586e568ec
Reviewed-on: https://chromium-review.googlesource.com/292870
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
The SLEEP_MASK_SPI will not be cleared, if SPI received a bad data.
It is possible to block EC to enter deep sleep if AP send a bad
packet to EC before AP goto S3/S5. In order to ensure that deep
sleep can be enabled, clear SLEEP_MASK_SPI in chipset suspend hook
to avoid this situation.
BUG=chrome-os-partner:44170
BRANCH=None
TEST=manually
1. use AP console command to let AP enter S5:
> shutdown -h now
2. check the sleepmask in EC console.
> sleepmask
sleep mask: 00000000
Change-Id: Ib5f5c421c123d9a3c2cc6fead07c8fa515e452f1
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/294432
Reviewed-by: Rong Chang <rongchang@chromium.org>
When there is an interrupt event, N8 CPU will save PSW register to IPSW
register and clear GIE then jump to interrupt service routine. N8 will
restore PSW from IPSW after "iret" instruction (the above are purely
hardware mechanism).
Nested interrupt will occur if we set GIE again in interrupt context.
symptom:
power button pressed while LID open -> exception or unknown reset.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. Manually pressed power button x200.
2. Console "eflash" erase and write eflash OK.
Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f
Reviewed-on: https://chromium-review.googlesource.com/289437
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Modified i2c driver into controllers and ports to support I2C0 port 0/1 at
the same time.
Modified drivers:
1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions
used by i2c_wedge and i2c_unwedge.
2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func.
3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should
replace GLUE_SDP0/1 with DP80BUF.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/294015
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The SPS RX FIFO handler prototype changed from passing cs_enabled
to cs_disabled, but the callback function for the spshc command didn't.
Now it does.
The spshc command switches the protocol on the SPI Slave bus to
expect EC Host Commands.
BUG=none
BRANCH=none
TEST=manual
At the EC console:
spstpm off
spshc
On the build machine, with an FTDI cable connected to the SPS
input:
cd extra/ftdi_hostcmd
make
./test_cmds
Change-Id: I69294a977b83854c5f6348904330bf74416cc6ec
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293619
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch syncs up TPM2 sources into the build area when building
cr50 image. This relies on a specific directory layout so that the ec
makefile has access to the tpm2 source tree.
The sources are copied using rsync, the tpm2 library is a dependency
for the RO/RW elf images, and is declared to be a phony make target,
which guarantees that the tpm2 make is always run when cr50 image is
built.
Include files in board/cr50/tpm2 are necessary to be able to build
tpm2 code using the bare metal toolchain used for building ec code.
memory.h is in fact empty, it is easier to add it here than to wrap it
in conditional compilation at the source.
Make variables CROSS_COMPILE and CFLAGS are exported for the benefit
of the tpm2 makefile. ROOTDIR indicates where tpm2 library should look
for .h files not available from the toolchain.
CQ-DEPEND=CL:292946
BRANCH=none
BUG=chrome-os-partner:43025
TEST=make buildall -j succeeds;
when linked with the latest tpm2 source, the combined image
starts the tmp task and reacts to the host sending the startup
command (failing due to unplugged stubs).
Change-Id: Ia3fd260588558c2bacd724df9583052fa4660ca3
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292975
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
TPM command processing should not be happening on the interrupt
context.
This patch adds a skeleton of the task which handles TPM functions. It
initializes the TPM and then enters endless loop waiting for an event
trigger from interrupt, which happens when a valid FIFO message is
received.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=none yet
Change-Id: I63dce2762cc07370a05bf00bdf144c5d9eb6019b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289332
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The default receive FIFO threshold of 8 (meaning that 9 bytes need to
be received before receive IRQ fires) is good for high volume
transfers, when the amount of transferred data greatly exceeds the
threshold.
But in case of TPM transactions, which start with a 4 byte header and
then stall while the device processes it, the default threshold
guarantees delays on every transaction, as the receiver does not start
processing the header until 5 idle bytes are transferred to bring the
total number to nine.
The suggested solution is to allow to specify the receive FIFO
interrupt request threshold at run time, by adding this value to the
receive function registration API.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=verified that spstest still works fine.
Change-Id: I92517205a7d0d47893b702efa188eb524fb18a49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289331
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
npcx GPIO code calls out to an LPC function, which isn't defined on
platforms without LPC support.
BUG=chromium:520207
TEST=`make buildall -j`
BRANCH=None
Change-Id: I80c0d08fea4a2621df9646926959fc48af52a15a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/293013
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fixed bug during polling port 0x204 by BIOS.
We should set processing flag before reading command byte in ISR to prevent
EC_LPC_STATUS_FROM_HOST and EC_LPC_STATUS_PROCESSING bits are both low.
Modified drivers:
1. gpio.c: Add LRESET ISR.
2. lpc.c: Fixed bug during polling port 0x204 by BIOS.
3. flash_ec: Reset ec before flashing ec
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I8e557f2e2be41a7a9d40c03c775313b12668f283
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/291210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
The public sources look for board configurations in directories
named board/$BOARD/
Sometimes it's necessary to keep sensitive projects out of the
public view for a bit.
This CL allows board configurations to also appear in directories
named private*/board/$BOARD/
BUG=none
BRANCH=none
TEST=manual
First, ebuilds and "make buildall" seem to work just as before.
Second, I copied 24 of the existing boards (those without
board-specific #ifdefs in the code) into a private*/board/
directory, renamed them to something unique, and ran "make
buildall" again.
Both public and private boards compiled and passed their tests.
Change-Id: I977c23cb8e73e40677c8f329abca8bbc51fd53df
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Use new board-level hibernate GPIO state function to turn off LEDs in
hibernate.
BUG=chrome-os-partner:43807
TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console,
verify that LED remains off. Press power button, verify that board wakes.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id695df9b5e75514f8f807a894b63f71676b66f92
Reviewed-on: https://chromium-review.googlesource.com/292317
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new board-level function board_get_gpio_hibernate_state which can
optionally be defined to set the desired state of a GPIO during
hibernate.
BUG=chrome-os-partner:43807
TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console,
verify that LED remains off. Press power button, verify that board wakes.
BRANCH=None
Change-Id: Ica11554e231e88773c3e139fea4622377ebe1e42
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/292471
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
symptom:
Unexpected watchdog reset console message if watchdog is enabled.
The IPC value of pre-watchdog warning is in idle task.
duplicate:
set time_us = 0xff000000 when timer init, watchdog will reset after
about 18 seconds.
also fix:
reload the watchdog counter while flash write.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. enable watchdog.
2. no unexpected watchdog reset.
3. ectool "flashwrite 0x20000 ec.RW.bin" no watchdog reset.
Change-Id: Ife10c2ead9c76462a865e694543e862b387d3b49
Reviewed-on: https://chromium-review.googlesource.com/292071
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
