USB uses a special mode the trigger remote wake-up during host
suspend, by setting the K-state on the data differential pair,
and setting a bit in the USB config descriptor attributes field.
Let's enable that so that hammer can wake up host from S3.
BRANCH=none
BUG=chrome-os-partner:62325
TEST=Connect hammer to chell, put chell in S3. Press a key (or use
("kb 3 3 1; kb 3 3 0" in console), or touch trackpad =>
host wakes.
Change-Id: Ib7b1e9047e01869f07ddd771c9c9bc640eef10d6
Reviewed-on: https://chromium-review.googlesource.com/446240
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This follows the basics of what is decribed in
RM0091 Reference Manual 30.5.5 Suspend/Resume events .
We call enable/disable_sleep at suspend/resume, to make
sure the EC stays awake when USB is connected and active.
We also call clock_enable/disable_module, which is stubbed on
stm32f0, but can be used on other devices in the family.
This also fixes interrupt handling in usb_interrupt, by only
clearing interrupt bits that were handled instead of resetting
them all, which is racy, and can potentially lead to issues
if reset comes soon after a resume event.
BRANCH=none
BUG=chrome-os-partner:62325
TEST=build and flash hammer, connect to chell, suspend/resume,
and see that hammer prints USB suspend and USB resume lines.
Change-Id: Ie9d02fd4a114add3ebc98dc9393680bc9a64a522
Reviewed-on: https://chromium-review.googlesource.com/446239
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The command line option to trigger communicating with the cr50 over
/dev/tpm0 has been set to 'spi' originally, as SPI was the interface
to communicate with the TPM on first devices using cr50.
This is not technically correct, as many devices use i2c for this
purpose. Let's rename the command line option from 'spi' to 'dev' and
correct names and comments to reflect this too.
BRANCH=none
BUG=none
TEST=ran on a reef device:
localhost tmp # ./usb_updater -f --systemdev
Could not open TPM: Device or resource busy
localhost tmp # initctl stop trunksd
trunksd stop/waiting
localhost tmp # ./usb_updater -f --systemdev
start
target running protocol version 6
offsets: backup RO at 0x40000, backup RW at 0x4000
keyids: RO 0xaa66150f, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.16
localhost tmp # ./usb_updater -f -s
start
target running protocol version 6
offsets: backup RO at 0x40000, backup RW at 0x4000
keyids: RO 0xaa66150f, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.16
Change-Id: Ifbdd3618209ad9930e0678cf50e82a789ae5e2cd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/447781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit enables the use of the nvmem vars module. The console lock
state is migrated from using the long life scratch register, to nvmem
vars instead which will persist across power on reboots.
BUG=b:35586145
BRANCH=None
TEST=Flash a dev image. Lock the console. Remove all power from the
system. Power on system and verify that console is still locked.
Unlock the console, remove power from the system, power on the system,
verify that the console is now unlocked.
TEST=Repeat the above test, but using the nvtestvar console command
instead.
Change-Id: I03a2098bb0017cfca59889457a332eafb0e95db6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445804
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB),
which doesn't fit the layout requirement in config_std_internal_flash.h.
This CL hardcodes the layout and flash bank mapping.
BUG=chrome-os-partner:62372
BUG=chromium:694972
TEST=load on elm and manually enable write protect using flashrom
# flashrom -p ec:dev=0 --wp-enable
check ec console write protect option bytes, bank 31 is writable
> rw 0x1ffff808
read 0x1ffff808 = 0xff00ff00
> rw 0x1ffff80c
read 0x1ffff80c = 0x7f80ff00
BRANCH=oak
Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446176
The new option allows the operator to explicitly request the post
reset reboot instead of immediate reboot (which is now ignored by
production cr50 images).
Also sort option descriptions and move the colons where they belong
(after command line arguments requiring additional parameters),
BRANCH=none
BUG=none
TEST=running usb_updater with -b or -d without extra parameter causes
the return error code and the help message printed.
running
$ ./extra/usb_updater/usb_updater -p build/cr50/ec.bin
results in a proper image transfer, with the following reboot of
the chromeos device triggering cr50 reset and the new downloaded
image running.
Change-Id: I64328973a2dfac1b78262f1ffacd677e52956d27
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446939
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until we can understand and fix the reset loop when we enable
low power for the TCPC mux lets just disable that feature.
BUG=chrome-os-partner:63204
BRANCH=none
TEST=build and boot on eve, verify that TCPC does not get in
a reset loop when the system is off.
Change-Id: I646948066a76ab25758e437498f3fb7f533ba6a5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446592
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Our previous idea to cut Rd for many reset cases cannot work if cr50
consistently resets the EC by asserting the reset pin shortly after
power-on. Therefore, make a decision based upon whether battery-backed
memory indicates we previously negotiated a PD power contract as a sink.
If we previously did not negotiate a contract, or if power was removed
from the device (causing battery-backed memory to wipe) then we can
assume that we don't have an active power contract.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, run "cutoff" on the console, reattach AC, and verify
device successfully wakes. Also verify Rp is dropped on console 'reboot'
and F3 + power from RW.
Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443356
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch makes the battery led behave as follows:
Charge: Amber on (S0/S3/S5)
Full charge: Blue on (S0/S3/S5)
Discharge in S3: Amber on 1sec off 3sec
Discharge in S5: Off
Error: Amber on 1sec off 1sec
Discharge in S0: Blue on
BUG=chrome-os-partner:63202
BRANCH=none
TEST=Fully charge Electro, then the LED shows
with no charger in s0: blue
with charger in s0: blue
with no charger in s3: blinking amber
with charger in s3: blue
with no charger in s5: off
with charger in s5: blue
When not fully charged, the LED shows solid amber in s0/3/5.
Change-Id: Idbfbbf35b951ce73c06377f292746c8c1c3ce0fd
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446580
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ROLLBACK region will be used to store rollback information, and
can be protected independently of RW (it can only be protected when
RO is protected, though).
This is only supported on stm32f0 currently.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=on hammer (stm32f072)
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp all; reboot => RO+RW+RB protected
flashwp noall; reboot => only RO protected
flashwp rw; reboot => only RO+RW protected
flashwp rb; reboot => RO+RW+RB protected
flashwp norb; reboot => RO+RW protected
flashwp all; reboot => RO+RW+RB protected
flashwp norw; reboot => RO+RB protected
TEST=on reef, rb/norb commands not available
Change-Id: I45ffc66d91cf3699ecff025e5114c59a73dc8274
Reviewed-on: https://chromium-review.googlesource.com/430519
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In preparation for adding the rollback protection region, we
would like to be able to protect RW region independently from
ALL.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make BOARD=hammer
Change-Id: I790fee6f038d511bce0f768420141b885e1c8c67
Reviewed-on: https://chromium-review.googlesource.com/444528
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Make sure all public and private host commands starting with
EC_CMD_ and EC_PRV_CMD_ are properly formed
BUG=chromium:681240
TEST=manual.
Added following host commands and verified that they were flagged
#define EC_CMD_TESTA 1234
#define EC_CMD_TESTB 0xabcd
#define EC_CMD_TESTC 0x1ABCD
#define EC_CMD_TESTD 0xXEF01
#define EC_PRV_CMD_TESTA 1234
#define EC_PRV_CMD_TESTB 0xabcd
#define EC_PRV_CMD_TESTC 0x1ABCD
#define EC_PRV_CMD_TESTD 0XEF01
These were also flagged by the script
include/ec_commands.h:#define EC_CMD_ACPI_READ 0x80
include/ec_commands.h:#define EC_CMD_ACPI_WRITE 0x81
include/ec_commands.h:#define EC_CMD_ACPI_BURST_ENABLE 0x82
include/ec_commands.h:#define EC_CMD_ACPI_BURST_DISABLE 0x83
include/ec_commands.h:#define EC_CMD_ACPI_QUERY_EVENT 0x84
CQ-DEPEND=CL:445809
BRANCH=none
Change-Id: I4630d6a887ed289a68178e8f1a8f07f5141c80bc
Reviewed-on: https://chromium-review.googlesource.com/445811
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Eve should be able to use the low power idle mode for the npcx EC
to get lower power in S3, and in S5 before we enter hibernate.
BUG=chrome-os-partner:63026
BRANCH=none
TEST=build and boot on Eve, enter S3 or S5 and observe that
dsleep gets enabled after the 15 second console idle timeout.
Change-Id: I7ffb2f56dde1593ec5b041522aa62e075a69b4c9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446618
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The TPS61161DRVR used for keyboard backlight expects an input frequency
of 5 to 100 kHz but is currently only getting 100Hz.
With this change the keyboard backlight duty cycle curve behaves as
expected and you no longer need 50% duty cycle to get it to turn on.
Also the keyboard backlight does not need to be enabled in DSLEEP
since that is only possible in S3/S5, so remove the DSLEEP flag.
BUG=chrome-os-partner:61464
BRANCH=none
TEST=test brightness range in sysfs to ensure backlight is visible
at low settings.
Change-Id: I9737827ad4dbd39e342ad370aef46475c273a6bc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446617
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Add generic routines to read or write a byte to battery-backed RAM, and
implement vbnvcontext get/set using these routines.
BUG=chrome-os-partner:62952
BRANCH=reef
TEST=On reef, with subsequent commit, run "cutoff" on the console,
reattach AC, and verify device successfully wakes. Also verify Rp is
dropped on console 'reboot' and F3 + power from RW.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d
Reviewed-on: https://chromium-review.googlesource.com/444444
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The GPIOs on npcx are handled in banks of 8, and when processing
an interrupt for a particular bank the ISR is executed for each
GPIO in the bank that has a pending bit set.
If an interrupt in a bank is not enabled (but has fired before so
the pending bit is set) but another one in the same bank is enabled
and asserts, then the ISR both of the GPIOs will be executed because
they both have pending bits set.
This results in the ISR for a disabled interrupt getting executed
when it should not and leads to unexpected behavior.
Masking the GPIOs that are not enabled means only the ISR for the
explicitly enabled GPIOs in that bank will be executed.
Example: With the Eve board we have PCH_SLP_SUS_L on GPIO(6,2) which
is enabled at init time and is in the same WKINTG_1 bank as
TRACKPAD_INT_L on GPIO(7,1) which is not enabled, but I am working
on a patch to enable it. When going into suspend PCH_SLP_SUS_L asserts,
and that is causing the ISR for both PCH_SLP_SUS_L and TRACKPAD_INT_L
to be executed. If I try to use TRACKPAD_INT_L as a wake source from
DeepS3 this means the system immediately wakes after going to sleep.
BUG=chrome-os-partner:62224
BRANCH=none
TEST=With an additional patch to enable trackpad wake from S3 on Eve,
observe that the system can enter S3 and stay there instead of immediately
waking up due to the TRACKPAD_INT_L ISR firing when it is not enabled.
Change-Id: Idc66e22c93756faf6c4319980cfb8dfe63e0dfaa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/446524
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The idea of this flag is to be able to protect/unprotect only the
RW portion of the flash. In the (usual) case where ALL=RO+RW, with
no other region, this makes no difference compared to the existing
EC_FLASH_PROTECT_ALL_* flag, and this flag may not be supported.
This is necessary for futher work, where a ROLLBACK region is added,
so that RW/ROLLBACK can be protected/unprotected individually.
Only support for stm32f0 is added, as this is the target for hammer.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=build and flash hammer (stm32f072)
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp all; reboot => RO+RW protected
flashwp noall; reboot => only RO protected
flashwp rw/norw not available
TEST=enable CONFIG_FLASH_PROTECT_RW
build and flash hammer (stm32f072)
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp all; reboot => RO+RW protected
flashwp noall; reboot => only RO protected
flashwp rw; reboot => RO+RW protected
flashwp norw; reboot => only RO protected
TEST=build and flash reef (npcx)
flashinfo => RO+RW not protected
flashwp true => RO protected
flashwp all; flashinfo => all_now displayed
reboot => RO protected
flashwp rw/norw not available
Change-Id: Ica6f499cf2e8a9345b08ef52c915655a983ffe3c
Reviewed-on: https://chromium-review.googlesource.com/442265
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Saves a little bit of flash size:
Compared 167 of 167 files.
77 files changed.
Total size change: -3240 bytes.
Average size change: -42 bytes.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make buildall -j
TEST=hammer: 'flashwp true' works as expected
TEST=hammer+CONFIG_FLASH_PSTATE_BANK: 'flashwp true' still works
TEST=reef: 'flashwp now' sets all_now flag in flashinfo
Change-Id: Ic2fe8f0c67520afea276369fdf8c59e75e95208e
Reviewed-on: https://chromium-review.googlesource.com/444488
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Power-up sequence must bring up PWR_NE followed by RESETN according
to Figure 5-16 of the datasheet.
BUG=chrome-os-partner:63045
BRANCH=none
TEST=Test charging, external monitor, usb flash drive in s0/s3/s5.
Change-Id: I0e69f0fd0a06f3c828ca59172e0ca045cdc4f5d7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445934
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This marks decriptor length as byte accurate, by
aligning the "__usb_desc_end" label by byte rather
than short or word.
BUG=chrome-os-partner:62873
TEST=servo_v4 doesn't crash adb anymore
BRANCH=None
Change-Id: I643bae2c59e81ce0c03d9026f4a5d7933ba4c891
Reviewed-on: https://chromium-review.googlesource.com/442012
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch implements the board_hibernate() function for
poppy. When running on battery only and in G3 state, the board
should transition into PG3 after CONFIG_HIBERNATE_DELAY_SEC
BRANCH=none
BUG=chrome-os-partner:61098
TEST=Disconnect AC. Use hibernate command from EC console to put
system into hibernate. Wake up the system from hibernate using
power button press or AC insert. Alternatively Use hibdelay command
to specify the hibernate wait timeout. Put the system into G3.
After hibdelay seconds the board should hibernate.
Change-Id: Ie0fc10ad60f15d6f40cf46bbe8b6dc9493c19e79
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/446242
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add the option to use the PLL connected the 16Mhz HSI oscillator.
Fix the system timer pre-scaling when changing frequency:
- we need to generate an update event immediately as on a 32-bit timer it
might take a very long time before going an actual update event.
- we need to ensure that the OS timestamp is monotonic and sensible
across the frequency jump.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=manual, on STM32L4 console, do several gettime and compare against
wall time, switch to 80Mhz with 'clock pll', verify again gettime
against wall clock.
Change-Id: Ibddbd46173b7594d16fb07e4b57660a50c636568
Reviewed-on: https://chromium-review.googlesource.com/445776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Keep only the most compact version of the curve25519 code
and remove the remaining unused code for easier compilation.
Do the minimal changes to make it compile in the EC code base,
there should be no real functional changes.
Re-use the wording from BoringSSL include/openssl/curve25519.h for the
header.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62991
TEST=run x25519 on host (ie 'make run-x25519')
and the STM32L4 target:
make BOARD=eve_fp PROJECT=x25519 TEST_BUILD=y
./util/flash_ec --board=eve_fp --image=build/eve_fp/x25519.bin
execute 'runtest' in the console.
Change-Id: I13dbe453eff39b461effb1b3ffa549afc1749fef
Reviewed-on: https://chromium-review.googlesource.com/444187
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Adam Langley <agl@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Import the implementation of the curve25519 public key cryptography
from BoringSSL.
It's the unmodified crypto/curve25519/curve25519.c file from the
repository at sha c034e2d3ce16df5f89134515bc113eb4f3a28e0e.
(current HEAD of chromium-stable branch)
It will be used as a primitive to implement a Diffie-Hellman exchange.
The test code in test/x25519.c is also imported unmodified
from BoringSSL crypto/curve25519/x25519_test.cc.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62991
TEST=with follow-up CLs, run curve25519 test vectors
on host, MEC1322 and STM32 targets.
Change-Id: Ie497f78249f505e32d8e025b0537e82bf4476298
Reviewed-on: https://chromium-review.googlesource.com/444186
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The TPM SPI protocol adds flow control capability, but it is
impossible to enforce it by software, software implementations need
additional means of informing the master about the slave status.
Let's follow the i2c slave driver example and use the interrupt line
from the H1 to the SOC to generate a low level pulse every time
receive data processing is completed.
BRANCH=none
BUG=none
TEST=to benefit from this patch some changes on the SOC side will be
required.
Change-Id: I576233598e98e01a007dff6b973fd96ea5ea551c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/446048
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously, wiping the TPM would wipe all of NvMem, however, it really
should only clear the TPM's NvMem space. This commit adds a function to
clear a given NvMem user's space and makes the TPM only clear its space.
BUG=chrome-os-partner:61597
BRANCH=None
TEST=Add code for using nvmem vars, create a test variable, add a user
to snappy, unlock the console, verify that the user is no longer present
on the system and the test nvmem var still exists.
TEST=make -j buildall
Change-Id: Ic98baa5166a1ef9ae76e910b1b9ab100300e947f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/445803
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
All host commands must be 4-digit uppercase hex digits.
The current ACPI host commands are defined as follows:
#define EC_CMD_ACPI_READ 0x80
#define EC_CMD_ACPI_WRITE 0x81
#define EC_CMD_ACPI_BURST_ENABLE 0x82
#define EC_CMD_ACPI_BURST_DISABLE 0x83
#define EC_CMD_ACPI_QUERY_EVENT 0x84
BUG=chrome-os-partner:63190
TEST=make -j buildall
100bd248 R __host_cmd_0x00000x0080
100bd254 R __host_cmd_0x00000x0081
100bd260 R __host_cmd_0x00000x0082
100bd26c R __host_cmd_0x00000x0083
100bd278 R __host_cmd_0x00000x0084
BRANCH=none
Change-Id: I48ad9c179454eb237018377023bae10a79c7799e
Reviewed-on: https://chromium-review.googlesource.com/445809
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch introduces a delay between accepted cr50 firmware upload
attempts. The next attempt to write into the same or lower address in
flash would be accepted no sooner than in 60 seconds after the
previous attempt.
This would prevent a rogue user from wearing the flash by repeated
uploads to the same address.
This limitation is not imposed by dev images (those compiled with
CR50_DEV=1).
BRANCH=none
BUG=chrome-os-partner:63098
TEST=verified that attempts to update soon after the previous update
result in the following error message issued by usb_updater:
sending 0x2d8b8 bytes to 0x4000
Error: status 0x9
Modified usb_updater to send one random pdu twice. Observed the
same error message.
Change-Id: Idca55ad091d09daaddd0a4cad5b1f871af1ede93
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445496
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Let's not allow downloading older images when in prod mode.
When the received chunk is destined into RO or RW header, verify that
the chunk's version is not lower than the current running version.
Also, if the chunk is not properly aligned with the header, verify
that it does not overlap with the header in any way.
BRANCH=none
BUG=chrome-os-partner:63098
TEST=verified that older images are rejected by prod images, and newer
and current level are accepted.
Verified that dev images still allow to downgrade.
Change-Id: I19c74f1d1bb5469cc935293a5841405149a968f6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444831
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is the recommended futility signature type for new boards.
BRANCH=none
BUG=chromium:690773
TEST=Flash hammer, RW image checked correctly
TEST=futility show --type rwsig \
--pubkey build/hammer/key.vbpubk2 build/hammer/ec.RW.bin
Change-Id: Id8648199891fdd4df63ecb599e0c5e927bc861d0
Reviewed-on: https://chromium-review.googlesource.com/441549
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The code deciding which partition to choose properly determines which
one is newer, but invariably populates the cache with the second one,
when both partitions are valid.
This is obviously wrong, on top of that there is no need to check both
partitions' validity, if the newer one checks out.
BRANCH=none
BUG=chrome-os-partner:60555, chrome-os-partner:61972
BUG=chrome-os-partner:61716, chrome-os-partner:61234
BUG=chrome-os-partner:61167, chrome-os-partner:60555
TEST=successfully ran
$ ssh 192.168.1.102 suspend_stress_test --suspend_min 10 \
--suspend_max 10 --wake_max 10 --wake_min 10
for more than 300 cycles (it still is going)
Change-Id: I02d9bb062b9edbbb9787a95ba760872e09ff2761
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/445356
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Current code puts key at the end of the first half of flash, which
may not match the actual RO section size (e.g., it might be PSTATE,
not RO). This makes sure the key to be at the end of RO section, and
signature at the end of RW section, no matter the actual layout
being used.
However, the (deprecated) usbpd1 image type assumes that flash is
equally split between RO and RW, so we do not change that.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=make BOARD=hammer -j && deploy
TEST=make BOARD=hoho -j && \
futility show --type usbpd1 build/hoho/ec.bin
Change-Id: Ia02e927f9128d6ec3d0b780c28312e0d18835d72
Reviewed-on: https://chromium-review.googlesource.com/426100
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Presently the CR50_DEV make variable is loaded: it enables debug
extensions in the produced cr50 image AND requires that the image is
signed with the key from the signing fob.
In fact these are two independent requirements: it is possible to use
an image built with CR50_DEV set for a dev H1 which does not require
fob signing.
A proper indication of the need to use the signing fob would be the
fact that H1_DEVIDS is defined, as it means a that node locked image
is being produced.
Images built without H1_DEVIDS set can be used on H1s which run with
the dev RO and as such do not need to be node locked, they are
signed with a well known key from util/signer/loader-testkey-A.pem.
This patch also tweaks passing the H1_DEVIDS variable to the shell
when altering the manifest. Without this tweak H1_DEVIDS definition as
make command line argument (as opposed to environment variable) was
not making it into the subshell invoked by make.
BRANCH=none
BUG=chrome-os-partner:62457
TEST=ran the following:
- built cr50 images with H1_DEVIDS defined in the environment and
in the command line, observed that the properly signed prod
image is produced (boots on a prod H1 in node locked mode).
- verified that adding CR50_DEV=1 to H1_DEVIDS in either
environment or the command line produces a properly signed
DEV image.
- verified that specifying CR50_DEV=1 alone in either environment
of command line produces a DEV image which does not require fob
signing.
Change-Id: Ied65a0bc50926aa5b6fa65e51805c2368522dcf2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434926
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Cr50 on x86 will run normally enter deep sleep and then wake up
immediately. When the AP turns off it stops pulling up the i2cs signals.
When cr50 enters deep sleep it sees that the i2cs signals are low then
wakes up immediately. After resuming cr50 will remain awake for 20 then
enter deep sleep. At this point it will remain asleep.
This change disables i2cs_sda and scl as wake pins when entering deep
sleep. Just like ARM these tpm signals are not in use when the device is
off. We have other signals to detect when the system leaves s3 or s5, so
we should rely on those.
We need this change because we want cr50 to fully enter deep sleep when
we run suspend resume tests. Right now the AP does not sleep long enough
for cr50 to enter the second deep sleep.
BUG=none
BRANCH=none
TEST=turn off the AP and make sure cr50 doesn't resume from deep sleep
immediately. run suspend_stress_test -c 5000 and verify cr50 enters deep
sleep and resumes correctly. verify dioa9 and dioa1 are enabled as wake
pins on resume
Change-Id: Ided8b2b7d5455650bca1e8d781063d092fb74c43
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/443389
Added interrupt handler for CABLE_DET signal on both port 0/1. This
allows us to define CONFIG_USB_PD_TCPC_LOW_POWER.
BUG=chrome-os-partner:63067
BRANCH=none
TEST=Connected USB mouse, keyboard and USB stick to both ports and
verified the devices were recognized and attached properly. Verified
that ports 0/1 always worked with blackcat typeC charger.
Change-Id: I4d8a8bdba4f95e73333e2e01f11fe1d48453a2fe
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/444315
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
