There are two different types of suspend states that are supported on
x86 platforms -- S3 and S0ix. When AP enters S3, the chipset state is
identified as CHIPSET_STATE_SUSPEND. On the other hand, when AP enters
S0ix, the chipset state is identified as CHIPSET_STATE_STANDBY. There
are several components within the EC e.g. charger state machine, usb
pd task, motion sense task that take actions based on the chipset
suspend state (and checked only for CHIPSET_STATE_SUSPEND until
now). In order to ensure that different EC components do not have to
worry about checking for all the different types of suspend states
that are supported, introduce a new combination
CHIPSET_STATE_ANY_SUSPEND which is a combination of
CHIPSET_STATE_SUSPEND(S3) and CHIPSET_STATE_STANDBY(S0ix).
BUG=b:69690699
BRANCH=None
TEST=make -j buildall. Ruben verified that with this change, EC power
consumption in S0ix drops from 7.85mW to 6.59mW on Soraka.
Change-Id: I599a0ea2fe2f39132764a6068fa77c3aea02affa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/786919
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Usually, the max current and supply voltage of dedicated chargers
are not known to the EC.
This patch adds EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT, which
allows the host to change the max current and supply voltage of the
dedicated charge port.
BUG=b:64442692
BRANCH=none
TEST=make runtests && buildall. Boot Fizz and let coreboot set
the adapter current and voltage.
Change-Id: I29b3f5762f8b316ca363c23e230530cdf4ca207a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/769152
1. The original driver of OPT3001
a. didn't support to process the command of offset.
b. implemented command of range to setter/getter of Range Number Field
of chip.
But reffering to cros_ec_light_prox.c from linux kernel side, these two
commands are actually leveraged for in_illuminance_calib[bias|scale]
and these calibration factors should be applied into raw lux value read
from the chip.
2. Move ALS in Poppy / Soraka boards from ALS_TASK to MOTIONSENSE_TASK.
3. Mofify parameters of ALS in Reef board in order to adapt changes
here.
BUG=b:69236269
BRANCH=none
TEST=Manually test on the DUT.
Change-Id: Ic3b593feb3e4bc6da0bada6b5d614975f0cf2280
Signed-off-by: Marco Chen <marcochen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/774341
Reviewed-by: Shawn N <shawnn@chromium.org>
Originally, i2c passthru is limited to use I2C_XFER_SINGLE flag where
it can only read at most 255 bytes at a time. For application that
requires larger i2c bus reading, we change the flag setting and the
command protocol.
TEST=old ./touchpad_updater still works (previous protocol)
TEST=new ./touchpad_updater can get more than 500 bytes per transaction
TEST=Debug message only print when -d assigned.
./touchpad_updater -d
TEST=Manually change #define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6)
to #define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 4) and trigger
POWER_OF_TWO assertion.
BRANCH=none
BUG=b:35587174, b:63993891
Change-Id: Id75b11ea49ba89bab8e18af24d47219030c778c5
Signed-off-by: Chun-Ta Lin <itspeter@google.com>
Reviewed-on: https://chromium-review.googlesource.com/542716
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
GPIO60 (PMIC_INT) is currently only configured for INPUT. Tests showed
that INPUT | PULL_UP has lower power consumption so reconfiguring it
here.
BUG=b:64503543
BRANCH=none
TEST=manual
(on chroot)
$ make BOARD=soraka -j
$ ./util/flash_ec --board soraka
(on DUT)
$ powerd_dbus_suspend
(on chroot)
$ dut-control -p $PORT pp3300_dsw_ec_ma -t 10 | grep @@
> NAME COUNT AVERAGE STDDEV MAX MIN
> pp3300_dsw_ec_ma 5637 1.68 0.17 7.92 1.56
for comparison, without the change, the MIN is 2.00mA
Change-Id: I86407a1440765d040c39272480b185342597d52b
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/786720
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
V5A was enabled in deep sleep state to allow wake from base in deep S3
state. Now that poppy and variants don't plan to use deep S3, this
change is no longer required.
BUG=b:69053636
BRANCH=None
TEST=Verified following:
> ectool i2cxfer 3 0x30 1 0x41
Read bytes: 00
> ectool i2cxfer 3 0x30 1 0x2a
Read bytes: 00
Change-Id: Ice8cabf5ecac3851400af5fef43821f596bc5224
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/786789
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
board_has_working_reset_flags was added to poppy/soraka to work around
a hardware issue in early revisions where reset flags would be lost on
PMIC reset. This issue should not occur for nautilus. Hence, get rid
of the function.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: Ib281c17e476bbf52dce055718c7faf61eb6ff507
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/784773
Reviewed-by: Philip Chen <philipchen@chromium.org>
Jerry pointed out that certain GPIOs which are 1.8V are set as 3.3V in
gpio.inc. Fix these gpios by add GPIO_SEL_1P8V flag to the gpio
description:
GPIOD1/I2C3_SCL0
GPIOD0/I2C3_SDA0
GPIO36 ACCEL_GYRO_INT_L
BUG=b:69481600
BRANCH=None
TEST=make -j BOARD=soraka. Verified that screen rotation works in tablet mode.
Change-Id: Ifbc474846aff0760f0b183a9cfeef2790738ca79
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/780142
Reviewed-by: Jerry Parson <jwp@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
With the upcoming change to add a new command to get/set/clear host
events and masks, it seems to be the right time to bump up the host
events and masks to 64-bit. We are already out of available host
events. This change opens up at least 32 bits for new host events.
Old EC commands to operate on host events/masks will still deal with
lower 32-bits of the events/mask. On the other hand, the new command
being added will take care of the entire 64-bit events/masks. This
ensures that old BIOS and kernel versions can still work with the
newer EC versions.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall. Verified:
1. hostevent set 0x4000 ==> Sets correct bit in host events
2. hostevent clear 0x4000 ==> Clears correct bit in host events
3. Kernel is able to query and read correct host event bits from
EC. Verified using evtest.
4. Coreboot is able to read correct wake reason from EC. Verified
using mosys eventlog list.
Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/770925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the SMP and Celxpert batteries for Robo systems, following
battery cutoff, there is a race condition resulting from a failed
sb_read operation when the battery status is read. If this read fails,
then the flag battery_report_present is reset to 0. Since this flag
gets set in a hook task deferred callback, if the sb_read fails after
battery_report_present is set, but before batt_pres is set to BP_YES,
then the deferred call would not be restarted. This results in the
battery_is_present call returning BP_NO indefinitely.
To fix this condition, this CL ensures that
battery_report_present_timer_started is cleared for any case that
could result in BP_NO. This addressed both this corner case and makes
redundant a previous change that was put to handle the case where the
battery is disconnected and reconnected while the system remains
powered. The CL also adjusts the timer to 0.5 sec so that in the event
it has to be called twice, it doesn't exceed the previous 1 second
timer and delay boot time even longer.
BUG=b:69151530
BRANCH=coral
TEST=With the DUT powered, removed and reconnected the
battery. Ensured that the battery again reports present.
Bitland also verified that with this CL they can no longer reproduce
the issue.
For the corner case, had additional debug console prints.
(Note this is with 1 second timer)
The deferred call is started.
[0.156135 battery timer hook call]
This shows where the sb_read error happens in batt_init()
[1.085627 Battery FET: reg 0x0018 mask 0x0010 disc 0x0000]
[1.092251 battery: pres 0, prev_pres 0, cutoff 0, init 1, rep 0]
[1.160969 battery will now report present]
This shows where the batt_report present gets cleared
[1.184993 ******** batt_report_present 1 -> 0 *****]
[1.185840 Battery read status failed]
[1.186540 report = 0, batt_init 1->0: stat = 0x200c6bea 1 get 1]
[1.187544 battery: pres 0, prev_pres 0, cutoff 0, init 0, rep 0]
[1.193796 Battery read status failed]
[1.194886 battery: pres 0, prev_pres 0, cutoff 0, init 0, rep 0]
batt_init() no longer returns 0, so deferred call is restarted
[1.290559 Battery FET: reg 0x0018 mask 0x0010 disc 0x0000]
[1.292942 battery timer hook call]
battery reports present now
[2.293436 battery will now report present]
Change-Id: I89d69cf133365affc4cc538328daeaaf9ac05ed9
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/773623
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
(cherry picked from commit 535080115d20dc223dab6288c5fea02da67c8e9c)
Reviewed-on: https://chromium-review.googlesource.com/782599
Commit-Ready: Scott Collyer <scollyer@chromium.org>
These functions are not used by usb_i2c.c on chip/stm32, let's
move them to board/cr50 which is the only place where they are
used.
BRANCH=none
BUG=None
TEST=make buildall -j
Change-Id: I8c1b292838b8dbee9a9001add9332e0add80c342
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/778749
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
It was recently identified that when we do a software based battery
cutoff and leave the system in cutoff state for > 25-30 seconds, then
both FG and battery enter shutdown/ship mode. In order to get the
battery out of this state, charger needs to provide VBAT >
Vstartup. However, with the current implementation of
battery_is_present, if EC is unable to talk to the battery i.e. i2c
commands to read battery status fails, then battery_is_present returns
BP_NO indicating that the battery is not present. This results in
charger state machine setting 0V and 0A to the battery, thus causing
the BGATE to be switched off.
In order to wake the battery from such condition, it is necessary to
provide pre-charge current and minimum voltage to ensure that BGATE is
switched on and VBAT > Vstartup is provided.
This change updates the battery_is_present algorithm to:
1. Check if battery is physically present. If not, return BP_NO.
2. If battery is present now and was present before when we checked,
then return BP_YES.
3. If battery just changed status to BP_YES, then check its disconnect
status. If EC is unable to read disconnect status, then return
BP_NOT_SURE. This allows the charger state machine to provide
precharge current and minimum voltage.
4. If EC is able to read disconnect status, try reviving it if
necessary.
5. Return BP_NO if battery is still disconnected or is cutoff or not
initialized.
6. Else return BP_YES.
BUG=b:69329874
BRANCH=None
TEST=Factory verified following:
1. Recovery from software based cutoff : Pass 10/10
2. Recovery from hardware based cutoff : Pass 10/10
3. Recovery from hibernate : Pass 10/10
4. Recovery from critical battery condition : Pass 10/10
5. Boot-up in case of no battery : Pass 10/10
Change-Id: I248705f87469a8d6604da1b1919492766499dd73
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/776024
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Change the names to generic touchpad_* functions, instead of
vendor-specific names. Makes it a little easier to add drivers
for other touchpads.
Also fix console_channel.inc to add the channel whenever any
touchpad is used.
BRANCH=none
BUG=b:68934906
TEST=make buildall -j
Change-Id: I6d268db5ebd53db272fb2ee7bbf06bbe80845734
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/778750
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Not needed since we're using the SN5S330.
BUG=b:69140019
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: Id8fa17e1e20ac805405fc6e48e481ceade1a1981
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/777823
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Nearly every board had a buttons array defined in which its contents had
the standard volume buttons. This commit creates a single common
buttons array that can contain the standard volume buttons and recovery
buttons. If a board has volume up and down buttons, they can simply
define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with
the standard definition. The buttons are active low and have a 30 ms
debounce period. Similiarly, if a board has a dedicated recovery
button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the
buttons array with a recovery button.
BUG=chromium:783371
BRANCH=None
TEST=make -j buildall.
TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume
buttons still work.
Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/773794
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Disable CMD_IDLE_STATS and USB_PD_LOGGING for gru in order to make
more code space for upcoming 64-bit host event support
BUG=b:69329196
BRANCH=None
TEST=make -j BOARD=gru
Change-Id: I5fca66d13224e077b157b0768ba0264948ab6a0d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/775876
Reviewed-by: Shawn N <shawnn@chromium.org>
This change switches the SS lines off in the main USB mux.
There has been some general flakyness regarding USB3 peripherals
and this change might address it.
BUG=chromium:718075
BRANCH=None
TEST=lsusb -t indicates 5000M before, 480M after.
Change-Id: Id201fb20dc6489c4a071cb1c9c0624d7aa54652d
Reviewed-on: https://chromium-review.googlesource.com/509130
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This is required to allow bumping up of host events to 64-bit by making
space in the rodata. CL 770923 had initially used GPIO_SHORTNAMES, but
HOSTCMD_ALIGNED seems to be a better option.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall
Change-Id: I63699f9cec244925c031d81f50889851c6da8b5c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771931
Reviewed-by: Shawn N <shawnn@chromium.org>
Disable ACCELSPOOF and FLASHINFO to save some space. This is required
to support 64-bit host events.
BUG=b:69329196
BRANCH=None
TEST=make -j buildall
Change-Id: I364adb1e224c2084398b4ee5bb9fd24a1c542e0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771997
Reviewed-by: Shawn N <shawnn@chromium.org>
On Nautilus, we use two ps8751b TCPC chips.
According to the latest schematic (link is in the bug),
we'll place two TCPC chips separately on different I2C ports.
BUG=b:69017605
BRANCH=none
TEST=build/flash nautilus rev0, and confirm PD charging from one
USB-C port works.
Change-Id: Iab7402023f148d478cba249aaf83a23675a7137b
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/758336
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Created Meowth symbolic link to Zoombini.
Modified Zoombini gpio.inc and board, etc. files to
compile a Meowth EC image with the correct gpios.
BUG=b:69133424
BRANCH=none
TEST=make BOARD=meowth and BOARD=zoombini
runs with no errors
Change-Id: Ib34d956efa89ae125de1ce7f8799162c74df0122
Signed-off-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-on: https://chromium-review.googlesource.com/762039
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to avoid runtime 64-bit left shift, check for extpower and
add two separate calls to host_set_single_event rather than
calculating the parameter at runtime. This avoids the requirement of
runtime logical shift for 64-bit.
BUG=b:69329196
BRANCH=None
TEST=make -j BOARD=samus
Change-Id: I64cacf6253878ed7d69f6b17baeb6c27c470378a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771854
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This reverts commit 1f767e3e91.
This is required to ensure that PMIC VR decay is enabled before
SLP_S0# is asserted. Else, the setting does not take effect and hence
results in higher power consumption.
BUG=b:69337192
BRANCH=None
TEST=make -j buildall. Verified by adding prints that VR decay enable
happens before SLP_S0# is asserted.
Change-Id: I0353f70c65ebe673b0e1b5ddbae2bb04368308cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add espi control module for it83xx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell.
2. console command "kbpress 1 4" to test keyboard data.
(board code for espi module test on CL:392587)
Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d
Reviewed-on: https://chromium-review.googlesource.com/394471
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Configure GPIOs to match grunt proto v1.1 schematic.
Change EC chip to npcx7m6f.
Minimal board.c/h, just enough to build.
BUG=b:64935726
BRANCH=none
TEST=make BOARD=grunt
Change-Id: I1a1f581c7ee7b80808c0dde179bc3ee0d69f960e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/754302
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Support protection of regions that aren't aligned to a power of 2 by
using two MPU entries, and taking advantage of the sub-region feature.
Also protect code RAM from being overwritten, on parts that use external
storage.
BUG=chromium:782244
BRANCH=None
TEST=On kevin, call:
mpu_protect_data_ram();
mpu_protect_code_ram();
mpu_enable();
Verify that first call results in the following update_region params:
addr: 0x200c2000 size: 0xc01d
Decoded: Protect 24K region
Verify that second call results in the following params:
addr: 0x100a8000 size: 0xc021
Decoded: Protect 96K region
addr: 0x100c0000 size: 0xf01b
Decoded: Protect remaining 8K region
Also verify that writes to beginning and end of code ram region trigger
data access violation after enabling protection.
Also verify that sysjump fails.
Change-Id: Ieb7a4ec3a089e8a2d29f231e1e3acf2e78e560a1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/757721
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Similar to coral and poppy/soraka devices, configure
USB_C{0,1}_PD_RST_L to be GPIO_ODR_HIGH since nautilus uses parade
TCPC on both ports.
BUG=b:69198785
BRANCH=None
TEST=make -j BOARD=nautilus
Change-Id: If76cf0588744b3adcfd75f4e2ebe0ea9e721683d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/767071
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reference CL:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/762066
The reset line for the parade TCPC on port 1, has an external 1k pull
up resistor. However, the gpio.inc description for this line was set
to OUT_LOW which results in a short reset pulse. This can lead to an
external charger seeing an unattach event and dropping VBUS. On Soraka
systems with certain chargers this results in a continuous reboot loop
when no battery is connected.
Changing the default state of this line to ODR_HIGH prevents reset
from being pulled low until the EC is intializing the TCPC and fixes
the continous reboot loop issue when no battery is connected.
BUG=b:69198785
BRANCH=None
TEST=On a Soraka system, verified that connecting Lenovo Type C
charger on Parade port did not result in reboot loop when no battery
is connected. Earlier this same setup resulted in continuous reboot loop.
Change-Id: I5138e129431ee4f0c1c6ceaaac5ab288c3ab6233
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/767070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch allows Fizz to switch the power source from a type-c
charger to a barrel jack adapter if the system is in S5.
BUG=b:38321259
BRANCH=none
TEST=Verify the following with 45W and 60W type-c chargers:
1. Boot Fizz with a type-c charger
2. Go to S5 if not already.
3. Plug in a BJ adapter. Fizz boots to S0 using BJ power.
Also verified other boot modes are not affected:
1. Auto boot on BJ insert
2. Auto boot on Type-C insert
3. Recovery boot on BJ
4. Recovery boot on Type-C
5. Stay off if it's previously S5
Change-Id: I86aa0fe6e403bcbacfe396997d897111ffcf8e74
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/706251
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The reset line for the parade TCPC on port 1, has an external 1k pull
up resistor. However, the gpio.inc description for this line was set
to ODR_LOW which results in a short reset pulse. This can lead to an
external charger seeing an unattach event and dropping VBUS. On some
Coral systems with certain chargers this results in a continuous
reboot loop when no battery is connected.
Changing the default state of this line to ODR_HIGH prevents reset
from being pulled low until the EC is intializing the TCPC and fixes
the continous reboot loop issue when no battery is connected.
BUG=b:68226308
BRANCH=coral
TEST=Using Robo system tested with the Lenovo Type C charger and
verified that the system can boot up without a battery when connected
to port 1. Bitland also verified this change in their test setup and
found no failures.
Change-Id: Ia16fe8cf770dc91da479497d234a2b6f9679b878
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/762066
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There are two Type-C ports and a DC Jack on GLKRVP. Added code
to allow system to boot from DC Jack also. This helps to boot
the device without Type-C connector during early stage of
software development.
BUG=b:69005234
BRANCH=glkrvp
TEST=GLKRVP can boot to OS without battery and DC Jack attached.
Also VBATA is set to battery voltage max.
When DC-Jack is present Type-C port is not enabled and
vice-versa.
Change-Id: I0fe5631c40490c56fba6ed5f3ad7ba7f5248460a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/757874
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
