Commit Graph

9 Commits

Author SHA1 Message Date
Mary Ruthven
61e0653261 cr50: add basic rbox support
This change modifies the behavior of RBOX by blocking the key0 and key1
output, when the power button is pressed. It also adds support for
printing debug statements when various RBOX interrupts are triggered.

BUG=none
BRANCH=none
TEST=On cr50 test board verify key0 and key1 out are not asserted unless
the power button is pressed.

Change-Id: I67a3c1b8009279015bdc87bcf0995cffa9ab6f03
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341470
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
2016-04-29 16:07:13 -07:00
Mary Ruthven
d281308b48 cr50: Detect debug cable and switch the PHY
This adds support for RD Detection on cr50. It can be used to detect a
debug device and signal the controller to switch from the AP PHY to the
to CCD PHY. When RDCC1 and 2 no longer detect the debug device, then
the controller switches back to using the USB to AP PHY.

BUG=chrome-os-partner:50700
BRANCH=none
TEST=change the value on RDCC1 and RDCC1 and check that the usb
controller connects to the right PHY.

Change-Id: Ice01a45a31fe1932945f89df2e3b851f4d287a17
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338454
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
2016-04-13 20:10:38 -07:00
Mary Ruthven
59c03bc4c6 cr50: enable use of multiple UARTs
cr50 has three UARTs that it will be using. This change modifies the
uart api to specify which uart to use.

BUG=chrome-os-partner:50702
BRANCH=none
TEST=change the interrupts and CONFIG_UART_CONSOLE to see that the
different UARTs can be used.

Change-Id: I754a69159103b48bc3f2f8ab1b9c8b86cea6bea5
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333402
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
2016-03-31 14:53:54 -07:00
Nadim Taha
c8484a9138 Cr50: Fixed soft resets on silicon.
Fixed the peripheral clock enable definitions and enabled the low speed
timers.

BRANCH=none
BUG=none
TEST=Tested soft resets on silicon.

Change-Id: Ie63e5732e5bead174abda89e5c5069b818212e9b
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324843
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
2016-02-01 21:17:22 +00:00
Gwendal Grignou
ff550b0e1a stm32: Enable 3rd SPI interface
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.

BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.

Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
2015-07-30 19:58:09 +00:00
Sheng-Liang Song
c12181d9af cr50: Added PMU driver
- Porting from cosmo code base.
- Support clock initialization

BRANCH=none
BUG=chrome-os-partner:33813
TEST="make buildall -j; Verified on RevA1 Chip"

Change-Id: I59e2bb133968d408acde44a3082e1b3b8f4bbbff
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/236394
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
2015-03-21 00:29:14 +00:00
Bill Richardson
806ba91ea4 Cr50: Update/refactor for new HW release
This is fairly large change set to accomodate a new hardware
release. There are enough differences to require refactoring the
registers.h file. Autogenerated constants are now in gc_regdefs.h
and all constant names begin with GC_, while register names are
defined in registers.h and begin with GR_.

Yes, I know the new header files are wider than 80 chars, but we
agreed that was okay in some cases if it makes them more readable
(see commit 3500c28).

BUG=chrome-os-partner:33423
BRANCH=none
TEST=make buildall -j

Build and run on the development board.

Change-Id: I21bd88c490f4f359ad17b5af9d17d8caca8dc9e4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230513
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
2014-11-18 23:52:08 +00:00
Bill Richardson
f154a8b95d cr50: Update TODO comments with new bug numbers
Just changing comments, no code.

BUG=chrome-os-partner:33432
BRANCH=none
TEST=make buildall -j

Change-Id: Ibffda40bff23a8c685feaef30a85e19157566245
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229860
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2014-11-14 23:56:44 +00:00
Bill Richardson
86c7e2e90a Add initial support for cr50 SoC
The serial console works. Nothing else is implemented yet.

BUG=none
BRANCH=ToT
TEST=make buildall -j

To build,

  make BOARD=cr50 hex

Testing the result requires a development board. I have one. It
works with HW revision m3.dist_20140918_094011

Change-Id: I718d93572d315d13e96ef6f296c3c2796e928e66
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226268
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2014-10-31 22:32:50 +00:00