This patch adds an interrupt handler for a tablet switch and an init
hook to enable the interrupt.
The handler does the typical tasks for convertible devices: 1. sets
tablet mode then 2. disables peripherals if tablet mode is on.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77298177
BRANCH=none
TEST=buildall. Verify on Nami.
Change-Id: If7fb5ea15f388d2b6084d800d2bc05efafd1945e
Reviewed-on: https://chromium-review.googlesource.com/1043057
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This patch refactors motion_lid so that EC can decide to use lid angles
to set tablet mode at run time.
Then, it implements board_is_lid_angle_tablet_mode to enable the feature
for Nami and Vayne.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:77298177
BRANCH=none
TEST=Verify on Nami.
Change-Id: Ib717911a16fe031aa6c6ede731e6aa722d32d022
Reviewed-on: https://chromium-review.googlesource.com/1024914
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
PD is enabled so don't need it.
BRANCH=none
BUG=b:74395451
TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests:
* Verified USB boot
* Plugged adapter to port-0/port-1/both and saw charging
* Plugged USB device to port-0/port-1/both and saw sourcing VBUS
* Plugged adapter to one port and USB device to another port
* Plugged USB disk to port-0 and booted into kernel
* When AP off, not sourcing VBUS to USB device
* Rebooting AP still works
Change-Id: Ib878960fb302d85549735a395f75cc8d045d45f2
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1042621
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Port 0:
TCPC: ANX3429
PPC: SN5S330
BC1.2: PI3USB9281
Port 1:
TCPC: PS8751
Power switch (sink): NX5P3290
Power switch (source): NX20P5090
BC1.2: PI3USB9281
Charger: ISL9238
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Did "gpioset EN_PP5000_A 1" before the folllowing tests:
* Plugged adapter to port-0/port-1/both and saw charging
* Plugged USB device to port-0/port-1/both and saw sourcing VBUS
* Plugged adapter to one port and USB device to another port
* Plugged USB disk to port-0 and booted into kernel
* When AP off, not sourcing VBUS to USB device
* Rebooting AP still works
Change-Id: Icde5e24c2cda3d0f2046486528a210af84befcca
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/969701
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
When we write a 0 to the register it actually prevents
future calls from correctly determining if the OCM is
present.
BRANCH=none
BUG=b:79123179
TEST=board with OCM still reports ocm after multiple anx_ocm 0 calls
Change-Id: I3899e8999483518fb42ddbd044d29e32fc3380f3
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047830
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Update the fingerprint match event to include the index of the template
which matched.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:77516790
TEST=on ZerbleBarn, enroll 5 fingers and do matching from the console,
see the proper finger index in the trace.
TEST=on Meowth, check unmodified biod still works for match with the
updated MCU firmware.
CQ-DEPEND=CL:*621808
Change-Id: I5be77ba65ce232989606274aba9a6c20841d533c
Reviewed-on: https://chromium-review.googlesource.com/1047267
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
In npcx5 series, there is no other chip generation and npcx's system
driver fixed the first character of revision array as 'A'. But in npcx7
series, there are two chip generations and it's better to show chip
generation information by 'version' console command.
In this CL, we used SRID_CR to distinguish the generation of npcx7
series. It also adds the support for NPCX787G in system_get_chip_name()
since it is used on the version 1 of npcx7 evb.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Verified npcx5m5g, npcx7m6g and
npcx7m7wb on evbs by 'version' console command.
Change-Id: I7572b5688b4430c6febd21c25f36c3903fb97e27
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1046689
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The ACOK_OD is a required signal of the charging state machine. EC
can't always hold it low; however, it breaks the charging state.
Make it back to EC input. There are some side-efforts, mentioned in
the bug.
BRANCH=none
BUG=b:78035750
TEST=Plugged/unplugged AC when AP is on/off.
TEST=Verified the power sequence still works.
Change-Id: I039af9cdb86cfb509f2580e6f57d82309825dac1
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1042620
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When we support the lowest power mode for Nuvoton in the next spin, we
will shed the TCPC/PPC power rail during hibernate. Before we drop the
power for the PPCs we need to ensure that Vbus is lower than the
hard-coded 6.8V dead-battery mode over-voltage threshold, otherwise we
will lock ourselves out of power.
BRANCH=none
BUG=b:79218851
TEST=verified that yorp renegotiates Vbus to 5V when entering hibernate
via ec `hibernate` cmd.
Change-Id: I4a98573eefb5757eea02dc48c64d5f9358b5e0b7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1047954
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Keep the timestamp of the latest power lost. Add a handler to wake
the chipset task to check if power lost stays low for a while (the
time between now and the latest power lost is longer than a period).
BRANCH=none
BUG=b:78455067
TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset
sequence and verified AP reset but not a transition S0 -> S5.
TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse
(see power_off function) to execute PMIC shutdown sequence and verified
a power-lost transition S0 -> S5.
Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2
Signed-off-by: Tom Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1028831
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This makes the EC listen to the AP_RST_REQ GPIO from AP. The rising
edge interrupts to trigger a hook to call chipset_reset().
As the hook task will be preempted by the chipset task, it adds a
flag bypass_power_lost_trigger to avoid triggering to S5 as the
chipset state machines sees power lost during the reset.
So far the chipset_reset() implementation is to do a cold reset;
will be revised to a warm reset after the PMIC registers are
reprogrammed.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Ran 'reboot' on AP console which toggles the GPIO.
Change-Id: I946cb029541ce018a8ed1ce25681d38998a7f4b6
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1023986
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On newer boards, FP_RST_ODL is no longer Open-Drain and has a 100k
pull-down. Drive it as push-pull.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:79277207
TEST=On ZerbleBarn, verify that the sensor comes up, has the right HWID
and can capture images.
TEST=On new boards, do the same.
Change-Id: I45e1ba41a7649e0682e3ea11dd0159f666286bba
Reviewed-on: https://chromium-review.googlesource.com/1049545
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
we need to configure EC_PROCHOT_ODL as an input because the EC isn't
driving it correctly. we changed the polarity of EC_PROCHOT for atlas
and similar boards, but the EC codebase has this hard-coded as
active-high.
this is a short-term fix until we implement a more general PROCHOT
"polarity" feature.
BUG=b:78911901,b:79266467
BRANCH=none
TEST=checked voltage drop across in-line resistor on EC_PROCHOT and
AP can now run above 400MHz
Change-Id: I8c3224c62ea7af4f386062d39c248d418e73fa53
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1045556
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
the isl9238 needs to see a higher PPVAR_SYS voltage than we were using
to avoid tripping Low_VSYS. Low_VSYS is one of the terms causing the
isl9238 to assert PROCHOT. its lowest default voltage threshold is
about 6.1v which is too close to the battery "minimum" that we were
using to set PPVAR_SYS. it's better to use the "normal" battery
voltage so the running-on-AC case is similar to the running-on-battery
case.
BUG=b:78911901
BRANCH=none
TEST=examined isl9238 regs to verify it is no longer tripping Low_VSYS
Change-Id: Iafc39e988a5af668c6cc1b5485841f6d659b1e8b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1043456
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
We add a configuration option to set the minimum shared memory
size (CONFIG_SHAREDMEM_MINIMUM_SIZE), so that the link will fail
if there is not enough IRAM left.
Also, we add 2 macros around shared_mem_acquire, that check, at
build time, that the shared memory size is sufficient for the
allocation:
- SHARED_MEM_ACQUIRE_CHECK should be used instead of
shared_mem_acquire, when size is known in advance.
- SHARED_MEM_CHECK_SIZE should be used when only a maximum size
is known.
This does not account for "jump tags" that boards often add on
jump from RO to RW. Luckily, RW usually does not do verification,
and does not need as much shared memory.
BRANCH=none
BUG=chromium:739771
TEST=make buildall -j, no error
Change-Id: Ic4c72938affe65fe8f8bc17ee5111c1798fc536f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1002713
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When cr50 resumes from deep sleep term_enabled is reset to 0, but not
all of the s3 termination settings are reset. Some of them are, because
some of the gpios are defined in gpio.inc and cr50 will handle setting
those up during init, but others like the sps pulldowns aren't. At this
point, the term_enabled setting does not actually match the state of
enabled terminations.
After deep sleep reset if the AP is on, ccd update state will try to
disable the s3 terminations, but term_enabled is 0, so s3_term thinks
they're already disabled and wont do anything even though some of the
terminations are actually enabled.
This change initializes all of the s3_term stuff to disable during hook
init. This way things are reset so they won't interfere with sps_init.
This will also make sure to align the system state with term_enabled,
before the ccd hook starts getting called. It is safer to start with
disabling the terminations, because it wont interfere with tpm
communication if the AP is on. If the AP is off, ccd_update_state will
re-enable the terminations around a second after init.
BUG=b:62200096,b:79214702
BRANCH=cr50
TEST=firwmare_Cr50DeepSleepStress.reboot on bob
Change-Id: I9a90c7f7703b1406b4c494db448a8ac84d040d1c
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1043152
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It was observed on yorp that connecting AC when EC is in hibernation
does not always reliably wake the EC up. The reason for this seems to
be that USB_C0_CHARGE_ON from ANX7447 is not asserting SINK_CTRL and
PPC does not pass through ACIN and thus ACOK_OD remains low.
This change ensures that SINK_CTRL is enabled on all the ports before
EC goes into hibernate state.
BUG=b:79173959
BRANCH=None
TEST=Verified that EC wakes up from hibernate reliably with AC
insert.
Change-Id: I14ff2c89511993fec53462ac606b92e5d9438739
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1043076
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Devices going into the testlab should have testlab mode enabled if
possible. Add support for enabling testlab mode on prepvt images.
BUG=none
BRANCH=none
TEST=make sure script complains when testlab mode isn't enabled on
prepvt image and passes ok when testlab mode isn't enabled on prod
images. Run testlab enable to make sure it works.
Change-Id: I623cac192fed31241d08a9d25e46e705cbbeb908
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1040357
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
When hibernate is run from EC console or using key combo, AP might not
actually be in shutdown state. Thus, add a call to force chipset
shutdown in board_hibernate and let AP drop down to S5.
BUG=b:79171681
BRANCH=None
TEST=Verified that hibernate with AP in S0 does not result in EC
waking back up.
Change-Id: I4103c51afb42944e05ec3965b421730fac3f867a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1041278
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Only USB port 0 is capable of device mode, so ignore data role
swaps to other ports.
BUG=b:78308749
BRANCH=eve
TEST=manual: ensure OTG pins are not asserted with data role swap
on port 1.
Change-Id: I07a331af11c3ce599a75517a5ba0ff2716987545
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1035424
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Configure switchcap every time we're about to change the signal,
just in case it forgot.
Feel free to revert this after b/77957956 is fixed.
BRANCH=none
BUG=b:77957956
TEST="i2cxfer r 0 0xd0 0x2" never shows 0x70, even after a bad brownout
(like "gpioset EN_PP5000_A 1" on an unreworked board)
Change-Id: I8994cd402ce96d8bf4e436dadfc0e572e7f77a85
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1024501
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
This is the power sequence for rev-0 board. Confirmed the behavior of
reprogramming the PMIC registers to enable the instant reset and
shutdown.
BRANCH=none
BUG=b:74395451
TEST=make buildall -j
TEST=Tried the following cases:
* Cold reset:
$ dut-control cold_reset:on sleep:0.2 cold_reset:off
Result: G3 -> S0
* Long power press to shutdown:
$ dut-control pwr_button:press sleep:8.2 pwr_button:release
Result: S0 -> S5 -> G3
* Long power press to power-on but then shutdown:
$ dut-control pwr_button:press sleep:8.2 pwr_button:release
Result: G3 -> S0 -> S5 -> G3
* Short power press to power-on:
$ dut-control pwr_button:press sleep:0.2 pwr_button:release
Result: G3 -> S0
* Console command: apreset
Result: S0 -> S5 -> S0
* Console command: power off
Result: S0 -> S5 -> G3
* Console command: power on
Result: G3 -> S0
* Console command: apshutdown
Result: S0 -> S5 -> G3
* Lid open to power-on:
$ dut-control lid_open:no sleep:0.2 lid_open:yes
Result: G3 -> S0
Change-Id: Ia9d44b1dccac66b5b580c08c6c1697ef5989b923
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/969702
Rename raw_read8 to st_raw_read8 and statically inline in the header
file. Removing the extern removes linker warnings when including this
header file without the driver, which happens in baseboard files.
BRANCH=none
BUG=none
TEST=including "driver/accelgyro_lsm6dsm.h" in c files that
do not link the actual driver will now compile.
Change-Id: I43f799a3b05b2343e012d43bdc9459d138ecf1b5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1042727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a state to indicate that a data role is actually disconnected and
notify the board-level data swap function with this state when a cable
is unplugged. This allows the board to clean up and restore any state
that may have been set up with a data role swap.
BUG=b:78308749
BRANCH=eve,poppy
TEST=manual on eve: plug in C-to-C cable, execute data swap on port 0
with 'pd 0 swap data' and ensure the OTG pins are asserted. Then unplug
the cable and ensure OTG pins are now deasserted.
Change-Id: I7d8fff22dd5836b4b5af54f0ede71ee1b6e40b5c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1035423
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Currently, sweetberry ocassionally throws Exception when
resetting the USB interface. This CL mitigates that by
- Use linearly back off algorithm with 10ms delay increment
before next reset attempt to avoid flooding the sweetberry
hardware with reset requests.
- Increase retry amount from 10 to 100
BUG=chromium:834252
TEST=No "Exception: ('Power', 'Failed to reset')" seen
Change-Id: Iaf039cb82760205d1747fd630387852b7cfd8f83
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1038788
RMA support through the cr50 console is only a part images starting with
0.4.5. Check that the prepvt version is greater than or equal to 0.4.5.
Versions 0.4.4 are greater than the prod version 0.3.3, but you can't
use it to do RMA open through the console. It can only be done through
the AP.
BUG=none
BRANCH=none
TEST=none
Change-Id: I7e08cc5dbc9f910686ea5917be755170c0587ee4
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1040356
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
We might use this in the kernel, so it's nice to have a diagnostic
command for it too.
BRANCH=none
BUG=chromium:836279
TEST=`ectool kbinfo` on kevin and scarlet
Change-Id: I746badf0d2be53d471592a2ca0d7b8ff8070f7a1
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1038729
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The new command line option is not used yet, it allows to set a flag
which would allow control verbose debug output in the future.
BRANCH=none
BUG=none
TEST=verified that -V command line option shows up in --help output
and is accepted.
Change-Id: Ie7becdb9c6964f7bb75e9917a02594d50c3c2693
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1036742
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Use the same script the rest of the EC codebase uses to generate the
version string.
BRANCH=none
BUG=none
TEST=built the new image and tried:
$ ./extra/usb_updater/gsctool -v
Version: v1.1.8258+6097a64f0, built on 2018-05-01 17:04:14 by ...
Change-Id: I63d2411872bbd38188f66f51b7ca8508fc74fa8f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1036741
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Add common defines in bip before we pull them into baseboard
to ensure that the diff of the move is clean.
BRANCH=none
BUG=none
TEST=bip builds.
Change-Id: I06333f2b1ad5d2d7bd057e5e8cd459199393ce1d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1038897
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
