The battery on kevin apparently requests 0A / 0V when extremely low, so
ignore this request and apply the pre-charge current.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Verify Kevin powers on with dead battery and battery charges as
expected.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I224f8ccd4f1d70d3a0f6f6e940fa6cbd80997fef
Reviewed-on: https://chromium-review.googlesource.com/361994
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
USB is only used for CCD. USB should not be enabled as a wakeup source
unless a debug accessory is detected, because that is the only USB
traffic we care about. The rest may be from other sources like the HID
interface or something else using those signals. This change disables
the utmi wake source when the debug accessory is attached and enables it
when it is connected.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=manual
The SPI_CS_L pin still gets triggered and will wake up cr50
before usb so disable wake up pins as a wakeup source.
Verify Cr50 goes to sleep and plugging in a SuzyQ will wake it
up and after removing it Cr50 will go back to sleep.
Change-Id: Ib97244016b0af244c340259915def9f4d8f97569
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360693
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
As of EVT2, remove I2C (TWI).
Use the pins for analog sensing of the battery level.
BUG=None
BRANCH=None
TEST=Sense the battery level and use the serial port.
Change-Id: I3d5d2401e61e6e7d203e933d2566f6f3cd65c054
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361546
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
Servo V4 rev2 has slightly different gpio mappings.
Note that this change will cause rev1 to not work.
Allow uservo routing before servod init. Further
work is needed on uservo port preinit as servod will
reset the port on startup, disconnecting uservo.
BRANCH=none
BUG=chromium:571476
TEST=Boot, use dut-control, see uservo.
Change-Id: I6436eed030cfdd329c5bd0cbca49038b268c2b71
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359620
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Regulate the system voltage by setting the charging voltage to battery
maximum in case of battery LEARN, Cut-off & No-battery conditions.
BUG=chrome-os-partner:55292, chrome-os-partner:55255
BRANCH=none
TEST=Manually tested on Amenia using console command charger.
Charging voltage is set to battery max in LEARN, Cut-off &
No-battery conditions.
Change-Id: I74bbab8174fd63b5f8439b8b35098db4a506d72d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/360681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before, as soon as the EC started booting, it would unconditionally boot
the AP (unless explicitly told not to. ie: "reboot ap-off"). However,
we weren't waiting for our power to settle which was causing some
brownouts. This would happen when trying to boot without the battery.
This commit causes the EC to inhibit powering on the AP until we have
sufficient power.
BUG=chrome-os-partner:55289
BRANCH=None
TEST=Flash EVT2; verify can boot normally.
TEST=Remove battery and insert charger. Verify that DUT can boot up.
TEST=Insert drained battery. Verify power on is inhbited. Plug in
charger and verify that DUT can power on.
Change-Id: Ifb40766fcc1d330674ec39de6d81174f92b6d658
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361005
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If our battery isn't able to provide enough power to the EC on boot, we
should not cut off our input power, regardless of dual role
determination or other charging policy.
BUG=chrome-os-partner:54944
BRANCH=master
TEST=Manual on Elm. Drain battery completely, attach USB-C charger,
verify that "Battery critical, don't disable charging" is seen on the
console and the EC doesn't brown out.
Change-Id: I7782d333da89b872e33ea31304f878ca490329cf
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/360781
Reviewed-by: YH Huang <yh.huang@mediatek.com>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Contains code for all the gpio tests so far. Code in
cts_task for th and dut is for testing purposes and
test result reporting will be updated in the next
patch.
BRANCH=None
BUG=None
TEST=Manual
- Connect handshake and gpio test lines between th and dut
- Build tests
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /def/ttyACM1' in another
- Flash boards
- All test results should print either passed or unknown
Change-Id: I7142fb87a6ce0a20c571cde608fbbe60e35898ea
Reviewed-on: https://chromium-review.googlesource.com/359935
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Having DIO A4, A8, and A14 connected to the spi master output pads
prevents reef from booting. We need to tristate those pins when spi ccd
is not in use.
This change disconnects those pins from the spi peripheral when spi is
disabled and reconnects them when spi is enabled.
BUG=chrome-os-partner:53582
BRANCH=none
TEST=manual
use 'pinmux' to verify DIOA4, DIOA8, and DIOA14 are set have
GPIO 7, 8, and 9 as their output sources when not using the usb
spi interface.
Check the usb spi interface still works.
Enable usb spi then disable ccd and check that the pins are
connected back to the non-peripheral gpios.
Verify the AP on kevin and reef can be flashed using servo.
Verify the AP boots successfully on both.
Change-Id: I85d70422a30da445076432d2bfc81960aeba8578
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357883
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Added code to get the VBUS level by reading the charger registers.
BUG=chrome-os-partner:55117
BRANCH=none
TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh)
registers are updated with the correct VBUS value on the
respective ports.
Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/359416
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently we have EEnoise(Decap Switching Noise) from LCD PWM
Kevin use LCD Backlight Driver IC and PWM Frequency from EC
Current 10kHz frequency can make switching Noise easily.
BUG=chrome-os-partner:55169
BRANCH=None
TEST=measuring noise reduced, verifying there was no influence
to LCD/digitizer/tsp
Change-Id: I1e65e56a19177dadba0110de5678669288a8555a
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/360003
Reviewed-by: Shawn N <shawnn@chromium.org>
When cr50 is not trying to do ccd, we dont need to monitor the devices.
Disable device state detection interrupts and the AP and EC UARTs.
BUG=none
BRANCH=none
TEST=gru and kevin monitor devices correctly when ccd is enabled, and
dont monitor anything when it is disabled.
Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356770
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
sync() involves 2 gpios on each board, each labeled
GPIO_HANDSHAKE_OUTPUT and GPIO_HANDSHAKE_INPUT on
their respective boards. They both start low,
then the th wiggles his line up and down, waiting
for the dut to mimic it.
BRANCH=None
BUG=None
TEST=manual
- Connect handshake lines to appropriate
pins on each board (pins found
in board's gpio.inc)
- Build tests
- Flash boards
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /dev/ttyACM1' in another
- They should each have printed
'successful sync'
Change-Id: I61233bca9605ba89c3628c2a65ca9013c56365ea
Reviewed-on: https://chromium-review.googlesource.com/359355
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Soft reset will not power down Cr50, so it wont assert EC_RST_L when it
reboots. This is a short term solution that fixes the cold vs warm reset
issue, but it does not fix the problem with all of all of the other Cr50
functions disappearing during warm reset. We will need to just reset the
TPM functionality on Cr50 to fix those issues.
BUG=chrome-os-partner:52366
BRANCH=none
TEST=Check asserting SYS_RST_L resets Cr50 and the AP and doesn't reset
the EC. Disable the Cr50 reset when SYS_RST_L is asserted, and verify
that the AP doesn't boot after the first reboot. Enable soft reset when
SYS_RST_L is asserted and verify the AP can successfully reboot many
times.
Change-Id: I7c0d0712ee6df59cfadd3975caf3503d44f3eff2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359342
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The AP no longer uses PHY0 to to interact with Cr50. Cr50 only uses PHY1
so dont switch the PHY when disabling CCD just release the usb.
BUG=none
BRANCH=none
TEST=After running 'ccd disable' the command 'usb' still returns PHY B,
but 'lsusb | grep 5014' on the host doesn't show any devices. When CCD
is enabled 'lsusb | grep 5014' shows a device on the host.
Change-Id: Icec0acc7a0d00f7eb56c6feef3ff4cf5a3f99735
Reviewed-on: https://chromium-review.googlesource.com/359931
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
cts.tasklist contains tasks run only for CTS. These tasks are added to the
tasks registered in ec.tasklist with higher priority. This design allows
board directories to be free from CTS stuff.
cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist).
If a suite does not define its own cts.tasklist, the common list is used
(i.e. cts/cts.tasklist).
BUG=chromium:624520
BRANCH=none
TEST=Ran the followings:
make buildall
make CTS_MODULE=gpio BOARD=nucleo-f072rb
make CTS_MODULE=gpio BOARD=stm32l476g-eval
Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359445
Reviewed-by: Chris Chen <twothreecc@google.com>
If the UART0 RX pad is not pulled up, cr50 will get held up on all of
the interrupts triggered by the low signal. This causes cr50 to reboot
continuously. UART0 RX was moved to DIOA13, which does not have an
internal pull up. This means we have to rely on an external pull up.
Because not having an external pull up on DIOA13 could prevent the
system from booting and UART0 RX is only used as an alternate debugging
mechanism from suzyq, we decided it is best for UART0 RX to be disabled
by default.
BUG=none
BRANCH=none
TEST=Connect UART1_RX to DIOA1 and test that it still accepts input.
Disconnect it from any pads. Verify the system boots normally and
console input from DIOA1 no longer works but the suzyq shell still does.
Change-Id: I68988c59cfce610cc6c360bf8dd9685e98ab12ff
Reviewed-on: https://chromium-review.googlesource.com/357881
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The first time you use this with a particular th,
connect only th and run ./cts.py --th
Then connect both boards and you can run
./cts.py to build/flash both boards.
BRANCH=None
BUG=None
TEST=manual
- Enter chroot
- Navigate to ec/cts
- Connect only th
- 'sudo ./cts.py --th'
- './cts.py -b'
- Exit chroot
- Connect both boards
- './cts.py -f'
Each board should flash successfully
Change-Id: Ib14fccabcd9fdad04f9b92817da597bc0dcb3d89
Reviewed-on: https://chromium-review.googlesource.com/358100
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This feature is inconsistent. Not all boards have such a symlink
(for a obvious reason).
This feature is fragile. It's most likely not tested and going to be
broken if not already. Developers won't like it if they have to test
two different ways to build boards before submitting patches.
This feature is not necessary. If you build EC in the standard way
(e.g. make BOARD=samus), these symlinks are not needed.
This feature is wasteful. Extra disk spaces are used and extra lines
are added to Makefile (increasing code complexity slightly).
BUG=chromium:626776
BRANCH=none
TEST=make buildall
Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359321
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have more than enough memory for that, and it makes it possible
to poll the logs from AP much more unfrequently.
BRANCH=oak
BUG=chromium:527904
TEST=make buildall -j
TEST=Boot elm, cat /sys/kernel/debug/cros_ec/console_log does not
miss any data.
Change-Id: I8cce88e39d00a94397b6fc852a371b4595870b24
Reviewed-on: https://chromium-review.googlesource.com/358181
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
elm EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD
is called every 100ms. Even when hcdebug is set to off, we still
get command errors.
BRANCH=oak
BUG=chrome-os-partner:55001
TEST=make buildall -j
TEST=Flash elm EC, see that output is fairly quiet.
Change-Id: I0a5ab2950911648e2e34f4ab1b6886e3e4bff774
Reviewed-on: https://chromium-review.googlesource.com/358438
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The EC asserts system reset on init, and Cr50 asserts ec_rst when it is
rebooted. Having the EC and Cr50 keep resetting each other prevents the
system from booting. We only care that Cr50 is restarted when the system
is restarted, so if it gets a system reset call when it is still
initializing everything it is okay to ignore it.
This change expects the EC to do a system reset on init, so it ignores
the first system reset. It will automatically enable the hard resets
two seconds after the board is initialized if it doesn't detect the
initial system reset.
BUG=none
BRANCH=none
TEST=reef and kevin can boot normally. Verify asserting sys_rst_l after
boot resets Cr50 and the rest of the system.
Change-Id: I198208950c526efd3ee0171812de3052785555f2
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358943
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This just adds a print statement to display board version at the
EC console the first time board_get_version() is called.
BUG=none
BRANCH=none
TEST=print shows up as expected with follow-up patches applied.
Change-Id: Ib7eae79a90bdaa58165aa5b102bc446f21a98963
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Proto had two pins for PROCHOT# - One to monitor and one to override.
Newer boards have only one pin that serves both purposes.
BUG=chrome-os-partner:54953
BRANCH=none
TEST=built and booted on reef
Change-Id: Ida4bc2766caf15562c26e7a4b792a07604361da2
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358940
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes corrections to the board ID values and also adds a small
multiplier to allow for higher-than-ideal voltages to match.
Currently we see values that are below the ideal value by about
2.5%, so it seems like a good idea to also allow slightly above ideal
voltage to account for variations in Vref or PP3300_EC that could
cause the calculated value to become higher than expected.
BUG=none
BRANCH=none
TEST=none
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia091fbbad7ffce2da9a04c48c7676ad9b4a08dea
Reviewed-on: https://chromium-review.googlesource.com/358614
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
The ADC multiplier and divider factors were lazily set to 1 when
the board support was first added, so the value was not scaled
properly.
The conversion formula is: Vi = CHNnDAT * (Vfs / 1024) where
Vfs = Vref = 2.816V for Reef.
BUG=none
BRANCH=none
TEST=added debug print and reading now approximately matches
what the voltmeter reads.
Change-Id: Ic60a8bc1d84c4f9a7b5664e9daddfa331b6a890c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358613
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Rename from V5A_EN to PMIC_EN.
The name V5A_EN came from Amenia where it controls both
5V_A-Rail and PMIC_EN.
Reef has a separate 5V_A-Rail control (EN_PP5000) and
an another GPIO pin for PMIC_EN.
BUG=chrome-os-partner:53666
BRANCH=none
TEST=buildall pass
Change-Id: Ic5e39b9811a6cf0e968c1d6262b9b9f849268ed4
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354767
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Since we are targeting a 45W solution, set max power to 45W.
BRANCH=none
BUG=chrome-os-partner:54519
TEST=Plug in Zinger and make sure 20V/2.25A is used instead of 20V/3A
Change-Id: Ie57a1df39f0cc642fe3644535aa1b5aa92f1ff35
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/358320
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch replaces a long standing stub. When the EC asserts this
signal, the CR50 must reset.
But this signal could be driven by CR50 itself as well, and in that
case the signal's assertion should not be causing the CR50 reset.
Ideally it should be possible to tell if the pin is configured as
output and ignore its assertion in that case. But there is no API for
checking the pin configuration settings at this time. An API function
is added to check if the AP Flash is being programmed, the GPIO
configuration access API is left for future enhancements.
BRANCH=none
BUG=chrome-os-partner:52366, chrome-os-partner:54982
TEST=issue 'reboot' command from the bash command line.
- verify on the cr50 console that it reboots along with the rest of
the device
- observe that reading of the NVRam spaces is still fully
functional, and Kevin can boot all the way up to the login
screen.
- try flashing AP firmware through CR50, verify that it succeed.
Change-Id: Ie4506238dc8b158b32121719a2db7fd232fd7d6c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357967
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow at least 10ms for the 'version' cap to charge in order to have a
voltage on the ADC pin that reflects our voltage divider circuit.
BUG=chrome-os-partner:54768
BRANCH=None
TEST=Manual on kevin. Run 'ver', verify that rev3 board is recognized as
version 3.
Change-Id: I1f3326f4c99a165d77363834d5671aa357a89007
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357970
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
For certain board configurations, KSI2 will be stuck asserted for all
scan columns if the power button is held. We must be aware of this case
in order to correctly handle recovery mode key combinations.
BUG=chrome-os-partner:54602
BRANCH=None
TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I03d76e1121107484f79520745858388f6cae096c
Reviewed-on: https://chromium-review.googlesource.com/357590
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The motion sensor drivers used to rely on #defines indicating I2C or
SPI port to tell which to use. However, these days the drivers get
that info passed in via the motion_sensor_t struct. Now this #define
simply decides whether to compile in SPI or I2C wrapper code. We
should eventually make it less confusing, but that's beyond the scope
for now.
BUG=none
BRANCH=none
TEST=reef motion sensor init works now
Change-Id: Ic38c57a6c070af391d2d4e2ec1a68ac90a377688
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356822
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a test that verifies RSA keygen from a fixed seed and
template from the TCG EK Credential Profile spec.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpmtest pass
Change-Id: I2f1cfb8460a0497c93079b89b9ff4e031eaff358
Reviewed-on: https://chromium-review.googlesource.com/356561
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
To achieve higher power efficiency, we want the input voltage to be as
low as possible. If the PD source advertise several choices over
PD_MAX_POWER_MW, choose the one with the lowest voltage.
BRANCH=none
BUG=chrome-os-partner:54519
TEST=Plug in Liteon charger and make sure 15V/3A is selected
Change-Id: I6157eb94a1cb45cd537acc79c377db2cff09d922
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/356317
Reviewed-by: Rong Chang <rongchang@chromium.org>
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
