Programmable Peripheral Interconnect is a shared resource.
This CL adds code for allocating PPIs to devices.
BUG=None
BRANCH=None
TEST=Modify the I2C code to use this PPI allocation code and test
I2C communication (using experimental MXT touch controller code)
Change-Id: I8ec27867d041982ef18e8515d6434c5de2c189c5
Signed-off-by: Myles Watson <mylesgw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361405
Commit-Ready: Myles Watson <mylesgw@chromium.org>
Tested-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
The battery on kevin apparently requests 0A / 0V when extremely low, so
ignore this request and apply the pre-charge current.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Verify Kevin powers on with dead battery and battery charges as
expected.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I224f8ccd4f1d70d3a0f6f6e940fa6cbd80997fef
Reviewed-on: https://chromium-review.googlesource.com/361994
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Pre-charge vs fast-charge mode depends on battery voltage relative to
VSYS. Rather than checking battery voltage (which may change), set
pre-charge and fast-charge currents whenever charger_set_current() is
called.
BUG=chrome-os-partner:55416
BRANCH=None
TEST=Manual on kevin. Verify system continues to boot with no battery.
Attach depleted battery, run "battery" and verify charger current is
~200 mA.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I68c06108c6d85ceede396294bedd1a017ddddd52
Reviewed-on: https://chromium-review.googlesource.com/361993
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
During pre-charge, batteries may request < 512 mA. Allow battery
charging at this low current, and only apply the 512 mA floor when no
battery is present.
BUG=chrome-os-partner:54821
BRANCH=None
TEST=Manual on kevin. Verify system continues to boot with no battery.
Attach depleted battery, run "battery" and verify charger current is
~200 mA.
Change-Id: Ia10e732a6b21587917ffa5e34035507f5be74dd3
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361589
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There was a mistake in the initial driver implementation
regarding the MDAC field in the measure register (address 0x04).
The header file and associated code defined this 6 bit field
to be the upper 6 bits of the 8 bit register. However, the
data sheet for both rev A and B silicon show this field as
being the lower 6 bits of this register.
In addition, when using this threshold to distinguish between
a Rd and Ra attach, the threshold test logic was backwards.
If the threhold bit is set, then it means the voltage is
higher than the 200mV setting and should indicate a Rd attach.
BUG=chrome-os-partner:54790
BRANCH=none
TEST=manual
Tested with Anker TypeC hub using known polarity (CC1). Previously,
would see CC2 be selected as the active polarity. This resulted
in USB PD state machine getting stuck in SRC_DISCOVERY due to
SRC_CAP messages not being received correctly. With the changes,
verified that correct CC polarity is always detected and results
in reaching SRC_READY state.
Change-Id: Ia522abdac31642ff99bbf13ccc73a0a77bbdb32d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361614
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Guenter Roeck <groeck@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Remove "task_disable_irq()" function call in EC_RTC_ALARM_CLEAR case.
Host command "RTC_SET_ALARM" with 0 second does not disable volume key interrupt.
BUG=chrome-os-partner:55401
BRANCH=none
TEST=check EC UART log message.
If you press volume up/down button
- Before HC 0x47 (RTC_SET_ALARM Command with 0 second)
Log : Button 'Volume Up/Down' was released.
- After HC0x47
Log : Button 'Volume Up/Down' was released.
GPIO volume key is still enable.
Change-Id: I8d8a4fa4927046b76a49ac4833b6a710db2e05be
Signed-off-by: younghun kim <young-h.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/361670
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Younghun Kim <young-h.kim@samsung.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This workaround ensure that we can successfully get
register latch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chrome-os-partner:55044
TEST=We simulate the delay time between first and second read,
and prove this method can avoid latch fail.
Change-Id: I7cafb53a8efbb2eee09af29d7365806dc0deb762
Reviewed-on: https://chromium-review.googlesource.com/358730
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
MKBP can now support buttons, so this commit adds the
keyboard_update_button() function which will be used to handle the
non-matrixed buttons.
BUG=chrome-os-partner:54976
BUG=chromium:626863
BRANCH=None
TEST=Flash kevin, press volume and power buttons and verify that
keyboard is still functional.
TEST=make -j buildall
CQ-DEPEND=CL:358633
Change-Id: I1c2d36d2113715cf6bd8c6fa7b26fe9253f6ac9f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/358634
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, the matrix keyboard protocol does not have support for
handling non-matrixed keys. This commit adds support for buttons which
do not appear in the keyboard matrix as well as switches.
Additionally, the keyboard FIFO is now just a general MKBP events FIFO
which MKBP events are free to use. Now, buttons and switches wil join
the key matrix event.
BUG=chrome-os-partner:54988
BUG=chrome-os-partner:54976
BUG=chromium:626863
BRANCH=None
TEST=Flash kevin, and verify that keyboard is still functional.
TEST=make -j buildall
CQ-DEPEND=CL:358926
Change-Id: If4ada904cbd5d77823a0710d4671484b198c9d91
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/358633
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
USB is only used for CCD. USB should not be enabled as a wakeup source
unless a debug accessory is detected, because that is the only USB
traffic we care about. The rest may be from other sources like the HID
interface or something else using those signals. This change disables
the utmi wake source when the debug accessory is attached and enables it
when it is connected.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=manual
The SPI_CS_L pin still gets triggered and will wake up cr50
before usb so disable wake up pins as a wakeup source.
Verify Cr50 goes to sleep and plugging in a SuzyQ will wake it
up and after removing it Cr50 will go back to sleep.
Change-Id: Ib97244016b0af244c340259915def9f4d8f97569
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360693
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Call rdd_attach or detach based on the current CC state and initialize
the debug map to the proper state.
BUG=none
BRANCH=none
TEST=reboot cr50 with suzyq plugged in and check ccd is initialized.
reboot cr50 with suzyq disconnected and verify ccd is disabled.
Change-Id: I61eb9f357ee4309030b06225502add4f5e43ac31
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361596
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
As of EVT2, remove I2C (TWI).
Use the pins for analog sensing of the battery level.
BUG=None
BRANCH=None
TEST=Sense the battery level and use the serial port.
Change-Id: I3d5d2401e61e6e7d203e933d2566f6f3cd65c054
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361546
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
Blink the LED in S3 as well as S0iX states so there is no user visible
difference in their behavior.
BUG=chrome-os-partner:55225
BRANCH=glados
TEST=Enter S0iX on cave and verify LED blinks.
Also verify that the LED still blinks in S3.
Change-Id: I883147b1c8e599de077c9f06e567a63d535a01f8
Signed-off-by: james_chao <james_chao@asus.com>
Reviewed-on: https://chromium-review.googlesource.com/359985
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Servo V4 rev2 has slightly different gpio mappings.
Note that this change will cause rev1 to not work.
Allow uservo routing before servod init. Further
work is needed on uservo port preinit as servod will
reset the port on startup, disconnecting uservo.
BRANCH=none
BUG=chromium:571476
TEST=Boot, use dut-control, see uservo.
Change-Id: I6436eed030cfdd329c5bd0cbca49038b268c2b71
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359620
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There's a new OTP change for the BD99955 and therefore the following
changes needed to be made.
- Change VFASTCHG_SET1 to 8.704V before CHG_EN is set to 1.
- Change VSYS_REG to 6.144V when starting Fast Charging.
- Change VSYS_REG back to 8.906V when Fast Charge is finished.
- Wait for 50ms to set CHG_EN to off (0) after Fast Charging has ended.
BUG=chrome-os-partner:55220
BUG=chrome-os-partner:55238
BRANCH=None
TEST=Flash kevin, plug discharged battery in. Plug AC in. `bd99955 r
0x11 1' and verify that VSYSREG is set to 0x1800 (6144mV).
TEST=`bd99955 r 0x1a 1' and verify that VFASTCHARGE is set to
0x2200 (8704mV).
TEST=Remove battery. `bd99955 r 0x11 1' and verify that VSYSREG is set
to 0x2300 (8960 mV).
TEST=Plug in battery and let charge to full. Verify that VSYSREG is set
to 0x2300 (8960 mV).
Change-Id: I5e5ca2cdcd4ead383416901c904df1e6fe5a9e28
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/360421
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Regulate the system voltage by setting the charging voltage to battery
maximum in case of battery LEARN, Cut-off & No-battery conditions.
BUG=chrome-os-partner:55292, chrome-os-partner:55255
BRANCH=none
TEST=Manually tested on Amenia using console command charger.
Charging voltage is set to battery max in LEARN, Cut-off &
No-battery conditions.
Change-Id: I74bbab8174fd63b5f8439b8b35098db4a506d72d
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/360681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Before, as soon as the EC started booting, it would unconditionally boot
the AP (unless explicitly told not to. ie: "reboot ap-off"). However,
we weren't waiting for our power to settle which was causing some
brownouts. This would happen when trying to boot without the battery.
This commit causes the EC to inhibit powering on the AP until we have
sufficient power.
BUG=chrome-os-partner:55289
BRANCH=None
TEST=Flash EVT2; verify can boot normally.
TEST=Remove battery and insert charger. Verify that DUT can boot up.
TEST=Insert drained battery. Verify power on is inhbited. Plug in
charger and verify that DUT can power on.
Change-Id: Ifb40766fcc1d330674ec39de6d81174f92b6d658
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/361005
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If our battery isn't able to provide enough power to the EC on boot, we
should not cut off our input power, regardless of dual role
determination or other charging policy.
BUG=chrome-os-partner:54944
BRANCH=master
TEST=Manual on Elm. Drain battery completely, attach USB-C charger,
verify that "Battery critical, don't disable charging" is seen on the
console and the EC doesn't brown out.
Change-Id: I7782d333da89b872e33ea31304f878ca490329cf
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/360781
Reviewed-by: YH Huang <yh.huang@mediatek.com>
Reviewed-by: Rong Chang <rongchang@chromium.org>
It's imported from test/interrupt.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=make buildall. Test passed on stm32l476-geval and nucleo-f072rb.
Change-Id: Ie948d284cebad60d97aab1512bb9e3af8838004e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360660
Reviewed-by: Chris Chen <twothreecc@google.com>
It's imported from test/hooks.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=make buildall. Test passed on stm32l476-geval and nucleo-f072rb.
Change-Id: I70673f2c0f8316a2b1fd9472eeb7db350fdc2d84
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360631
Reviewed-by: Chris Chen <twothreecc@google.com>
It's imported from test/mutex.c and adjusted to CTS.
BUG=chromium:624520
BRANCH=none
TEST=Test passed on stm32l476-geval and nucleo-f072rb. make -j buildall
Change-Id: I8cab0541ecbb1daa26b4d728fbd3e45e903ee512
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360600
Reviewed-by: Chris Chen <twothreecc@google.com>
Test functions are listed in cts.testlist and shared by th.c and dut.c.
This way, we can gurantee the two files are in sync. Also, cts.testlist
is used to count the number of tests automatically.
This allows us to use a for loop to execute each test.
BUG=none
BRANCH=none
TEST=build buildall
Change-Id: I0c811405134fad04f5c6914b1ac38835e212cbd2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359619
Contains code for all the gpio tests so far. Code in
cts_task for th and dut is for testing purposes and
test result reporting will be updated in the next
patch.
BRANCH=None
BUG=None
TEST=Manual
- Connect handshake and gpio test lines between th and dut
- Build tests
- run 'cat /dev/ttyACM0' in one terminal
- run 'cat /def/ttyACM1' in another
- Flash boards
- All test results should print either passed or unknown
Change-Id: I7142fb87a6ce0a20c571cde608fbbe60e35898ea
Reviewed-on: https://chromium-review.googlesource.com/359935
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
A new option is being added to the set of command line options, '-s',
once it is specified, the utility tries to update the CR50 using
/dev/tpm0.
BRANCH=none
BUG=chrome-os-partner:54992
TEST=emerge-gru ec-utils, copy /build/kevin/usr/sbin/usb_updater and
~/trunk/src/platform/ec/build/cr50/ec.bin to the DUT, try running
the update command on the DUT:
$ <path to>/usb_updater -s <path to>/ec.bin
observe in the end of the log:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvv
-------
update complete
bye
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
restart the cr50 and verify that it is running the new image.
Change-Id: Idb755328f911f3065f01df420488c7a1b4a32500
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358967
Reviewed-by: Andrey Pronin <apronin@chromium.org>
RDD is working reliably and defaulting to CCD makes it difficult to
display port functionality.
BUG=chrome-os-partner:52281
BRANCH=none
TEST=manual
run 'reboot ap-off' on the EC. Plug in a unreworked suzyq and
verify 'lsusb | grep 5014' doesn't show any devices
run 'powerbtn' on the EC and verify 'lsusb | grep 5014' now
shows a device.
Check that this works on gru, kevin, and reef.
Change-Id: If4a9fc2f8f874e602c28f8e397c9bf8ea6184b59
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360914
Reviewed-by: Bill Richardson <wfrichar@google.com>
Having DIO A4, A8, and A14 connected to the spi master output pads
prevents reef from booting. We need to tristate those pins when spi ccd
is not in use.
This change disconnects those pins from the spi peripheral when spi is
disabled and reconnects them when spi is enabled.
BUG=chrome-os-partner:53582
BRANCH=none
TEST=manual
use 'pinmux' to verify DIOA4, DIOA8, and DIOA14 are set have
GPIO 7, 8, and 9 as their output sources when not using the usb
spi interface.
Check the usb spi interface still works.
Enable usb spi then disable ccd and check that the pins are
connected back to the non-peripheral gpios.
Verify the AP on kevin and reef can be flashed using servo.
Verify the AP boots successfully on both.
Change-Id: I85d70422a30da445076432d2bfc81960aeba8578
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/357883
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When the debug cable is disconnected the a USB suspend interrupt is
triggered and puts the chip to sleep before rdd can detect a change on
the cc lines and disconnect from CCD. This prevents the DEBUG_STATE_MAP
from being reset to detect the debug connect and is left detecting the
disconnect. Since the debug accessory is already disconnected the RDD
interrupt will wake up the chip right after it goes to sleep.
The UTMI and PIN wake source still cause the chip to wake up before the
RDD interrupt, so disable those to test this change.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=Disable wake pin and utmi wake sources. Put cr50 to sleep. Attach a
reworked suzy q and make sure cr50 wakes up. Detach it and check that it
goes back to sleep. Do that a couple of times. Check CCD is still
enabled when the debug accessory is detected and disabled on
disconnect.
Change-Id: I58a012895bc874dcdd512aa84de9a917469f3139
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360234
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added code to get the VBUS level by reading the charger registers.
BUG=chrome-os-partner:55117
BRANCH=none
TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh)
registers are updated with the correct VBUS value on the
respective ports.
Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/359416
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the uart rx signal is not externally pulled high by the EC or AP,
the low rx signal triggers thousands of uart interrupts. At
initialization Cr50 does not know the state of those devices. If the
uart is initialized when the device is off these interrupts may prevent
Cr50 from booting on certain boards. This change does not enable the
uart until the device state is know. When the device state monitoring
detects that the AP or EC is powered on it will enable uart 1
or 2 and when it detects that it is powered off then the uart will be
disabled.
BUG=none
BRANCH=none
TEST=UART_CTRL registers are set to 0 for uart 1 and 2, and are changed
to 3 when the device state is on.
Change-Id: I43e847c6abb8507a86de92a5c226a79f3add7f97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360026
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The bit IRQ11B of register HIIRQC is meaningful only when PM Channel 1
is in PC87570-Compatible. In previous commit, we deprecate use of
PC87570 mode but set the bit unintentionally. This will not cause any
bug but may make confused when reading the code.
Modified sources:
1. lpc.c: CLear IRQ11B in register HIIRQC.
BUG=chrome-os-partner:34346
TEST=make buildall -j; verify on Wheatley
BRANCH=none
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Change-Id: I594222c29557add847a1f689859fdf558d64fdd3
Reviewed-on: https://chromium-review.googlesource.com/358536
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently we have EEnoise(Decap Switching Noise) from LCD PWM
Kevin use LCD Backlight Driver IC and PWM Frequency from EC
Current 10kHz frequency can make switching Noise easily.
BUG=chrome-os-partner:55169
BRANCH=None
TEST=measuring noise reduced, verifying there was no influence
to LCD/digitizer/tsp
Change-Id: I1e65e56a19177dadba0110de5678669288a8555a
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/360003
Reviewed-by: Shawn N <shawnn@chromium.org>
We need to (at least) build CTS for all boards & suites supported by CTS.
This will prevent our investment from accidentally being broken.
BUG=chromium:627252
BRANCH=none
TEST=make buildall builds CTS suites
Change-Id: Ib7bceaafd5e27ce9285b9d1bf35339bf6b04ba72
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359947
When cr50 is not trying to do ccd, we dont need to monitor the devices.
Disable device state detection interrupts and the AP and EC UARTs.
BUG=none
BRANCH=none
TEST=gru and kevin monitor devices correctly when ccd is enabled, and
dont monitor anything when it is disabled.
Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356770
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
