If the sn5s330 PPC is being used to detect VBUS presence
(CONFIG_USB_PD_VBUS_DETECT_PPC), then enable interrupts and call
usb_charger_vbus_change when VBUS_GOOD changes.
BUG=b:72007153,b:72007492
BRANCH=none
TEST=Connect 3A and 1A USB-A chargers to each of Grunt's USB-C ports,
check that BC1.2 detection is working:
With 1A:
> chgsup
port=0/1, type=7, cur=500mA, vtg=5000mV, lsm=1
With 3A:
> chgsup
port=0/1, type=7, cur=2400mA, vtg=5000mV, lsm=1
TEST=Boot Grunt to OS, then connect USB2 mouse or USB3 flash drive to each
of Grunt's USB-C ports. Devices do not work due to b:71772180, but gpioget
shows EC is setting USB_C0/1_BC12_VBUS_ON_L correctly.
Change-Id: Iffc352105a321997adb364b9fbb8bafef248c224
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887938
Reviewed-by: Jett Rink <jettrink@chromium.org>
Meowth also seems to take enough power when flashing without a battery.
Zoombini has a similar issue, and the fix is to wait 1s to let the
voltage level stabilize before flashing.
This commit just waits 1 second before flashing.
BUG=b:65694390
BRANCH=None
TEST=./util/flash_ec --board meowth; Verify it succeeds without a battery.
Change-Id: Ida34a7eb923187940afe05a32d200b48e71aaa9f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/894370
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Flash operations in do_flash_op() involve waiting polling for the chip
to complete the operation. If a concurrent operation is started while
another operation is in progress, flash gets confused and locks up.
Let's add a mutex to ensure that flash operation runs to completion
before another operation starts.
BRANCH=cr50
BUG=b:67651754
TEST=multiple times ran firmware update while the device was coming up
and saving TPM status in NVMEM. Observed no failures.
Change-Id: I777a38f8a63cf17d60edb11cc3f916a4ea904741
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/894180
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
- Add a vendor command that provides alert counter. Userspace can use
it e.g. for user metric analysis.
- Add 'alerts' debug console command. It provides information about
chip alerts: supported alerts, fuse status, interrupt status, alert
counter.
- Add 'alerts fire [INT]' command to fire a software defined alert
(globalsec/fwN where N is 0,1,2,3).
Signed-off-by: Anatol Pomazau <anatol@google.com>
BUG=b:63523947
TEST=ran the FW at Pyro and checked alerts data sent to host
Change-Id: I7cec0c451ed71076b44dad14a151b147ff1337e8
Reviewed-on: https://chromium-review.googlesource.com/817639
Commit-Ready: Anatol Pomazau <anatol@google.com>
Tested-by: Anatol Pomazau <anatol@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Boards with a PPC will use the PPC to discharge the VBUS line instead
of the TCPC or GPIO discharge path.
BRANCH=none
BUG=b:72179253
TEST=Fall time after device removal on grunt within spec now
Change-Id: I822923a1cedb32a20efc3610cce4437ade3387f0
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/886563
Reviewed-by: Edward Hill <ecgh@chromium.org>
Templates for USB isochronous implementation. Current implementation
only supports TX transmit. Example of usage can be found in CL:803414.
Basically, declare an USB isochronous interface by
USB_ISOCHRONOUS_CONFIG_FULL(<NAME>,
<INTERFACE_NUM>,
<USB_CLASS>,
<USB_SUBCLASS>,
<SUB_PROTOCOL>,
<USB_STR_FOR_INTERFACE_NAME>,
<USB_EP_NUM>,
<PACKET_SIZE>,
<TX_CALLBACK>,
<SET_INTERFACE>)
where <PACKET_SIZE> is size of each USB packet, <TX_CALLBACK> is called
when USB hardware has completed a packet. The buffer that USB is not
currently using will be passed to <TX_CALLBACK>, allow applications to
write next packet to it.
When a SET_INTERFACE packet is received, <SET_INTERFACE> will be called
with bAlternateSetting and bInterfaceNumber.
We will declare interface descriptor with bAlternateSetting = 0 and 1
for you, if you need more alternate settings, you need to declare by
yourself.
BUG=b:70482333
TEST=manually on reworked staff board
Signed-off-by: Wei-Han Chen <stimim@google.com>
Change-Id: Ic6d41da6ddd7945edf0bdfff55ede38a97661783
Reviewed-on: https://chromium-review.googlesource.com/818853
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
On VM-based builders, the nvmem unittest was sometimes missing the
10-second deadline, likely being stuck in slow I/Os.
Try to move the persistent storage files used for flash 'emulation' on
host from the build directory to a RAM-backed filesystem in /dev/shm
in order to mitigate this bottleneck.
Store the new backing files in a path like:
/dev/shm/EC_persist__mnt_host_source_src_platform_ec_build_host_nvmem_nvmem.exe_flash
in order to keep the properties of the old system:
subsequent runs of the same build will use the same persistent storage
but 2 different trees won't mix up.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:715011
TEST=make runtests
TEST=run the following command with and without this change:
'for i in 0 1 2 3 4 5 6 7 8 9 ; do time make run-nvmem ; done'
and see the average test time around 500 ms without the change
and around 320 ms with it on an idle and beefy workstation.
Change-Id: Ic2ff6511b81869171efc484ca805f8c0d6008595
Reviewed-on: https://chromium-review.googlesource.com/893380
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This allows the acpi_light sysfs entry to be populated with the actual
ALS data.
BUG=b:70290036
BRANCH=None
TEST=Flash meowth; read both illuminance values for the ALS devices
under iio and verify that they are both operational.
Change-Id: Ia22633629195d5bdeedc70a908ceca1411110b7d
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/888218
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In the system, RT946x is always powered by the battery.
So even in battery cutoff mode, the reg values on RT946X are not reset.
We don't want RT946x to supply VBUS when DUT boots, which could mess up
PD state. So we need to disable VBUS output when RT946x initializes.
BUG=b:72228350
BRANCH=none
TEST=Confirm OPA_MODE (bit0 in reg 0x01) is clear after RT946x
finishes initialization
Change-Id: I32795b3bea64860b164c14b06aa1cd2551ebd8a0
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/890028
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
rt946x_block_read() is not implemented right.
It not only makes rt946x_init_irq() fail but also put
RT946x i2c module in an erroneous state temporarily.
BUG=b:72228350
BRANCH=none
TEST=manually on scarlet rev3:
1)Insert Plugable USB-C hub w/o AC
2)Run cutoff command on ec console
3)Hold Pwr button for a few seconds to wake up DUT
4)Repeat 2 - 3 for 10 times without seeing PD loops
Change-Id: I9304617f924e44288483afca5ab1b2923eb68ff0
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/890027
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
It's no longer necessary to call board_tcpc_init() from PD tasks, since
HOOK_INIT completion is guaranteed before the task starts. Also, calling
board_tcpc_init() for each PD task without a port arg is a bad idea.
BUG=b:72229154
BRANCH=none
TEST=`make buildall -j`
Change-Id: I6fba07771693b8343568041960a263e02775a8fc
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/881538
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
stm32f0 has 20 bytes (not 20 words) of VBAT-backed RAM. Make more
efficient use of our limited storage to prevent trying to use storage
that doesn't exist.
BUG=b:71333840
BRANCH=None
TEST=Negotiate PD, run "reboot" on scarlet EC console, verify reset path
is taken in pd_partner_port_reset().
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie4c303b74a1b82b84ec971cdcc19c2b21a0032e7
Reviewed-on: https://chromium-review.googlesource.com/885461
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The logic of drawing as much current as possible when no battery
is connected (on the lid), and system unlocked, makes sense during
early bringup.
However, it will not work when the base is also connected, as we
did not implement the required no-battery logic in the base/lid
power allocation algorithm (nor do we plan to, as it is only
required during very early bringup, when we should not expect
power transfer between lid and base to work properly).
Also, we need to record input_voltage in
charge_set_input_current_limit, even when lid battery is not
present (yet), otherwise the algorithm gets confused and believes
no power is available.
BRANCH=none
BUG=b:71881017
TEST=Boot lux from dead battery and base connected, lux does not
attempt to drive OTG to the base.
Change-Id: I0cdd0956a82a724dbbf9c010760dcb956a58c1bf
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/874982
Reviewed-by: Shawn N <shawnn@chromium.org>
This is required to support mode-aware DPTF. Also, there is no need to
send mode change event in board specific code as that is already done
by dptf common code.
BUG=b:65467566
BRANCH=None
TEST=Verified that trip point temperatures get updated in the OS
depending upon the device mode.
Change-Id: I854628bcde755bdb1c6c1b73fbfa0948e1d7e420
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/887725
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Add BOARD_DEEP_SLEEP_DISABLED and BOARD_DETECT_AP_WITH_UART to
BOARD_ALL_PROPERTIES, so they will be updated after cr50 reboots.
BUG=b:35647982
BRANCH=cr50
TEST=test deep sleep on scarlet
Change-Id: I8999ae7c6c1dad6799b5fdb99ebf5d7618a21c2b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/882343
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Instead of fetching static battery information all the time, we
first fetch the dynamic information, and see if the flags changed.
If they did, refetch the static information.
This also covers the cases when the base is disconnected/reconnected.
BRANCH=none
BUG=b:71881017
TEST=ectool battery 1 shows correct static battery information after
plug/unplug.
Change-Id: I936983fc0fdc4dae0494e8a24f890927e30555dc
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/872813
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
the current 50ms delay between the capture and having the image
available was working (to some definition of it) on the current boards,
but we hit issues on the next revision of the board with new sensor
silicon (and somewhat different delay), let's put a larger 200ms delay.
This will be converted to waiting for the proper MKBP event (aka
EC_MKBP_FP_IMAGE_READY) when all the boards using this feature will have
MKBP events support validated.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:71770455
TEST=run 'ectool --name=cros_fp fpcheckpixels' on different boards.
Change-Id: Id1f2402ef85c903744054b00eeab0086221b4d7b
Reviewed-on: https://chromium-review.googlesource.com/888738
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Allow to have CONFIG_MALLOC defined for one partition and not the other.
The typical use-case is asymetric firmware whose small RO is typically
just an updater/verifier (and RW signature verification currently
doesn't like malloc as the memory initialization is done too late).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:72360575
TEST=make buildall
Change-Id: I67cc04cd11385d4c05556ea41ef674cb7a232e65
Reviewed-on: https://chromium-review.googlesource.com/885820
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
First version of the algorithm, some TODOs are left in the code
but this, generally, works reasonably well.
When charging, we allocate input current in this general order:
- Base system (fixed, low, number)
- Lid system (based on PSYS)
- Lid battery (estimating how much current the battery actually
requires)
- Base battery (similar estimation)
- Provide everything else to lid
When discharging, we generally:
- First discharge the base battery
- Then discharge the lid battery
BRANCH=none
BUG=b:71881017
TEST=Flash lux and wand, EC-EC communication works, adapter power
is split in a sensible way, and discharging works fine.
Change-Id: I8a4f87963962fc5466b2fedf1347eb4dadd35740
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659460
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Lux base detection is a little trickier than previous bases,
as the detection levels switch around when GPIO_EC_COMM_PD gets
enabled:
- When disconnected, low levels (~550mV) mean base got connected,
and high levels (~3300mV) mean base is still disconnected.
- When connected, low levels (~43mV) mean base got disconnected,
and high levels (~2346mV) mean base is still connected.
On reset, when base_status is unknown, we enable GPIO_EC_COMM_PD,
to be able to differentiate between connected and disconnected.
BRANCH=none
BUG=b:67029560
TEST=Connect lux/wand, check that base gets detected correctly.
TEST=Type reboot in EC console, base gets detected as well.
Change-Id: I742def8e378a93c08e2dcc155b06cbca814e7fd8
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/845543
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Some chargers don't respect the SRC.Open state within the 20ms allotted by
the usb spec. The LiteOn Charger seems to notice after ~120ms bumping to
200ms so we cutoff Vbus for even ill-behaved chargers. We expect to brown
out in the sleep.
BRANCH=none
TEST=LiteOn charge will disconnect now
BUG=b:72510370
Change-Id: Ief0e999ed52f39420eed5f07432273e741a14c7e
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/886833
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
We don't want the PPC to connect the CC lines from the
TCPC to the USB connector until the TCPC resistors are
set in a valid state (SINK initially).
If we connect the CC lines (happens in the ppc_init) before
setting the resistor values, some TCPC will be toggling the
CC line between Rp/Rd since it doesn't detect a cable yet.
In the dead battery charging case, connecting the toggling
CC lines to the charger can rail the CC lines to 3.3 V signaling
to the charger to disconnect Vbus, thus browning out the board.
BRANCH=none
BUG=b:71865251
TEST=Grunt powers on via usbc p0 with and without USB hub.
Change-Id: I8e78aa2af42075398fab89a2dccef5e7df27b260
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/882305
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
This chip controls the keyboard backlight. The backlight level is set
through PWM, but the chip needs to be enabled and configured before PWM
settings are recognized. This will be initially used for grunt and
zoombini.
BUG=b:69379749
BRANCH=none
TEST=In EC console for grunt: kblight 100; kblight 0
Change-Id: I5576d709687d8f61b5757485baa239ffd6b41a74
Signed-off-by: Benjamin Gordon <bmgordon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/879082
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
The way Nautilus battery checks the conditions of CHG/DSG FETs
are slightly different from the other smart batteries we use.
So the current implementation of battery_check_disconnect() doesn't work.
BUG=b:69016914
BRANCH=none
TEST=recovery from software-based battery cutoff 10/10
Change-Id: I88de64d8da55f0b57fbdde21d4529435841bdf76
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/882941
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
There are two versions of npcx7 EVB. This CL adds the definition
BOARD_VERSION (default is 2) in board.h. So we can include different
features or set CONFIG_* flags based on the value of BOARD_VERSION to
meet the default HW configuration of npcx7 EVBs.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change BOARD_VERSION to 1/2; "BOARD=npcx7_evb make";
Flash the image on EVB 1/2; make sure the EVBs bootup.
Change-Id: Id4556f702af8c26778a649addde7cf490b5301fc
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/873510
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
To support CR50 deep sleep mode:
In up-sequence, SYS_RST_L needs to remain asserted on the transition
to S5 and then deasserted on the transition to S0;
In down-sequence, SYS_RST_L needs to be asserted on the transition to S5.
This only affects Scarlet.
BUG=b:35647982
BRANCH=none
TEST=minitor SYS_RST_L pin to confirm it is toggled right
Change-Id: Ic73d39c531f9d28b2087a23d58613e98ec80dbd2
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/866115
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
