The current gpio_get_level() is pretty slow because it looks things up each
time. Add a new function to find out the register address and mask to use
to check the value for a particular GPIO.
Time-critical code can then use this to check a GPIO.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow;
Power on the board, hold power button for 10s and see that it powers off
Power control still works, thus GPIOs are functional
Change-Id: Ifc6c56f5cb811e0243e7712725a51948eabd42ab
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26175
Sometimes it is useful to get access to the flash directly, without using
flash_read(). Add a function to do this.
Since the range checking is done in every function in flash_common,
use the new function to do it for us. That way we get a slight (64 byte)
code size reduction.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow with SPI flash emulation, in U-Boot:
See that the 32KB of flash has been provided correctly.
Change-Id: I6622a24234edaed371dd5b9bf43d1f3974d55e39
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26174
The WWDG is not ideal for this purpose, since if we fail to handle its
interrupt withint 60ms or so, we get a reset. This can be a problem when we
are reporting a panic, since the uart output takes a long time.
Change to using timer 9, which is free, and make it print a watchdog warning
after one second.
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow; waitms 1200 and see that a watchdog timeout is
reported correctly.
See that the panic message is displayed in full without a reset happening
before the end.
Change-Id: Ifc3671098e1f3a7ef409b8d1fb919d22eaa90358
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26172
This driver was not refactored when the host_command changes were made,
although i2c was. Tidy this up.
SPI requests the command response immediately rather than going through
the task queue, since otherwise a response may take long enough that the
SPI master misses it altogether.
BUG=chrome-os-partner:10533
TEST=manual:
build and boot on snow; In U-Boot:
> sspi 4:0 240 20
See that it gets key messages back now
Change-Id: Ia2c24d4c8876fefedad4c02802f77e50d7159d03
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25982
Use two suitable GPIOs to implement a simple arbitration scheme.
Each side owns one of the GPIOs, which are normally pulled high.
When one side wants to use I2C as a master, it pulls its GPIO low,
waits for a short period to make sure that the other side is not
also pulling its GPIO low, and then goes ahead with the transaction.
When the transaction is over, the GPIO is released, thus freeing the
I2C bus up for use by the other end.
For simplicity the terminolgy used here is EC for us, and AP for the
other end.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I97d9fbd5aba8248c8c1240baaec17db22860665c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26142
This corrects a small bug where by the UG bit in EGR was
not getting set, so the shadow registers were not being
reloaded as the comments suggest they should be.
This is really only a minor clean-up. The timer appears to
work fine with or without the patch.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=timerinfo appears sane on Snow
Change-Id: I637e2fc1f5dbfa1e70d33f96c8bf38ac57cc7b2c
Reviewed-on: https://gerrit.chromium.org/gerrit/26520
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Simplify this code, so that it does only one pass of the response data,
calculating the checksum as it copies.
BUG=chrome-os-partner:10535
TEST=manual:
build for all boards
build and boot on daisy
see that keyboard still works
Change-Id: I8b0a2ce1632dd4c1ff54736fb636d9a5cf8c9214
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25981
This seems to be a hangover from the LPC protocol. We can send a result
just by sending a response with no data.
Drop this function and remove all uses of it.
Also use 'enum ec_status' instead of int, since this is the correct
response type.
BUG=chrome-os-partner:10533
TEST=manual:
build for all boards
build and boot on daisy
Change-Id: I93a029bd6ba8cec567b61af3b410bcead015b5c0
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25980
This drives the power LED for Snow (PB3) using TIM2 in PWM mode.
Since timer setup and manipulation is STM32-specific, the power LED
logic moved to to chip/stm32/power_led.c.
This also adds a "powerled" console command for testing.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:10647
TEST=Tested on Snow with powerled command, compiled for Daisy
Change-Id: I5a7dc20d201ea058767e3e76d54e7c8567a3b83c
Reviewed-on: https://gerrit.chromium.org/gerrit/26267
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Add a new function to dump the current dma state, and hide it behind
a more official-sounding CONFIG_DMA_HELP.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: I42fb101628e9044284a6b39447b0b1fc2d36587b
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26168
By subtracting the current dma count from the number of bytes originally
requested to be transferred, we can find out how many bytes have been
transferred so far.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: Ideee1ed27c08b56882f5d2095341fe04bbe9c34b
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26167
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This change fixes mutiple snow charging issues. Including:
- disable i2c host auto selection
- i2c_read8 got wrong output value
- pmu CHARGE_EN control workaround
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:11010
TEST=Only test on snow dvt with AP turned off
plug/unplug ac adapter and check charging led
check console command 'battery'
Change-Id: I29d554b3daa4cfc538bd5bf5ba5233976d381861
Reviewed-on: https://gerrit.chromium.org/gerrit/26529
Tested-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Chain TIM3/4 as the 32-bit timer instead of TIM2/3. This frees
up TIM2 to be used for other purposes.
BUG=chrome-os-partner:10647
TEST=Flashed onto Snow, stuff works and timerinfo output is sane
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Icdfe3596a15bc2ee8536f160b1f08ac3041b9193
Reviewed-on: https://gerrit.chromium.org/gerrit/26202
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Add a way for boards to permit or deny access to the I2C port. This
works in a board-specific manner.
All I2C master traffic requires that board_i2c_claim() be called
first. A dummy function is provided for boards which do not require
this.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I786d4ae17f1d798faf13b303b5389679fb6720cb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26141
This allows us to prepare a dma transaction in advance, and quickly
start it when needed.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: Ib7d843b2d3a5cd94b6025b9741db1794ebbcfda0
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26449
This reverts commit 7af4172be4afad9d576549721a82b3a47d701647 / Iac605b879b3556f33af5585b298ada6bc4f52c90.
This change bypassed the commit queue and broke daisy as a result.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I7a05ab42f71a901d167bde977f8a025c7ef62dfc
Reviewed-on: https://gerrit.chromium.org/gerrit/26379
Reviewed-by: David James <davidjames@chromium.org>
Tested-by: David James <davidjames@chromium.org>
This allows us to prepare a dma transaction in advance, and quickly
start it when needed.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Iac605b879b3556f33af5585b298ada6bc4f52c90
Reviewed-on: https://gerrit.chromium.org/gerrit/26166
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Simon Glass <sjg@chromium.org>
Rather than a channel number, use a pointer. Also we don't need a
return value, since this function cannot fail.
BUG=chrome-os-partner:10533
TEST=build and boot on snow
Change-Id: I9d7e567a9f3d496184fd28f0820ad798b1c43a28
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26165
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Access to dma is currently via a channel number. It is more efficient
to export a pointer to the dma channel since it avoids the conversion
on every API call. This helps, because dma is often on the critical
path.
Export the function to provide a pointer to a dma channel given its
number.
BUG=chrome-os-parter:10533
TEST=manual: build for all boards
Change-Id: I0318e59dbb1b9077f0445804692ca7ea99cf6581
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26164
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is ~4x as fast as flashing the entire EC image, and is similar to
the existing flash_link_a command.
BUG=none
TEST=from openocd prompt, flash_link_ro
Change-Id: I04160af3d7d70028f8d2789480094c283a1ce2ab
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26268
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
At present there is quite a bit of duplicated code. Create a new
i2c_transfer() function to take care of this.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I3672cc4ff9de4e2e0deaec2997590ee892ef09aa
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26140
When we are transmitting a response to the EC, we don't want to race
with the TX empty interrupt handler. So just disable I2C interrupt
during the transmission.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Lucas DVT, use the keyboard and see we are no longer getting
"bad checksum" in the kernel log.
Change-Id: Ic59532d1ac0a3eabb67ba0d498940986282bd87f
Reviewed-on: https://gerrit.chromium.org/gerrit/26162
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
- most events happen in the first 100us, we don't want to sleep to 2ms.
This introduces big delays. Just poll the 150us, then fall back to
sleep.
- restore properly the port state after master transfers.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On Lucas DVT, probe I2C signals with logic analyzer and manually
check them. Verify that the keyboard is still working with the charging
code enabled.
Change-Id: Ic0afde081d070ff6720d924469ecc7166bbc9e4c
Reviewed-on: https://gerrit.chromium.org/gerrit/26161
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
There isn't a good reason for doing things this way, so tidy up the
code and remove the TODO.
BUG=chrome-os-partner:10533
TEST=manual:
build and boot on snow
Test writing of flash still works using U-Boot command
Change-Id: I66a8f16072dc28f24c493af7674f7be5d838529c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26163
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Needed for EC software sync so the AP can verify the EC's RW code and
tell the EC to jump to RW when necessary. If the AP then decides it
doesn't need to stay booted, the AP can shut back down. (The AP
verifying the EC's code and/or shutting back down are NOT part of this
CL...)
Also add a Power+Refresh+DownArrow key combination which causes the EC
to reset WITHOUT powering on the AP; this will be needed for debugging
the AP power-on sequence.
BUG=chrome-os-partner:10892
TEST=manual
1) power+refresh+down -> ec reboots, system stays down
2) power+refresh+esc -> ec reboots, system to recovery
3) power+refresh -> ec reboots, system boots
4) hibernate, then open lid -> ec reboots, system boots
5) hibernate, then power button -> ec reboots, system boots
6) yank battery, then reconnect -> ec reboots, system boots
7) reboot ec -> system boots
8) 'sysjump A' when AP already booted -> system stays on
9) 'sysjump A' when AP shut down -> system boots
Change-Id: I65d2f7d9cca3acb84b76302cdcd8c8a800f03253
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26158
Don't check if we've jumped to this image (which preserves the reboot reason,
so was causing us to re-check).
BUG=chrome-os-partner:10890
TEST=manual
1) power+refresh; should see EC print [KB boot key 0]
2) sysjump A; should NOT see [KB boot key 0]
Change-Id: I46cc60358e1d1952484f52147787fee06e4ff69f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26155
Reviewed-by: Simon Glass <sjg@chromium.org>
Keyboard scan module now owns the recovery key state on all platforms.
And clean up a few comments to linux kernel style
BUG=chrome-os-partner:10890
TEST=manual
- Power on system. Should boot normally.
- Power+Refresh+D. Should turn dev switch on.
- Power+Refresh+F. Should turn dev switch off.
- Power+Esc. Should reboot system. Power button should power on normally.
- Power+Refresh+Esc. Should power on into recovery mode.
- Then press power to shut system down.
- Power button should power on normally (not back into recovery mode).
Change-Id: I4d16e1e8b039efeacbd41e8acec115844bc8457d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26147
Reviewed-by: Simon Glass <sjg@chromium.org>
And if RW B isn't enabled, it's not even linked.
BUG=chrome-os-partner:10881
TEST=on link, should be no B image, and 'sysjump B' should fail
On BDS, still should be A and B images
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: Icb2af07881cc7e28b9b877f45824486a22fde8d7
Reviewed-on: https://gerrit.chromium.org/gerrit/26116
This ensures the keyboard backlight will go off even if the chipset
shuts down due to overheating (or some other unclean shutdown).
(Also fixes inter-function line spacing to linux kernel coding style
and reformats a few comments.)
BUG=chrome-os-partner:10718
TEST=manual
1. power on system
2. turn on keyboard backlight (kblight 100 at EC console)
3. power off system (for example, via power button)
4. keyboard backlight should turn off
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I5bbcd1681ae9c972c9875e9c720617bdf51e3d64
Reviewed-on: https://gerrit.chromium.org/gerrit/26039
At this point, EC code requires EVT. If you still have a proto1,
here's what'll break:
1) Keyboard recovery mode checks refresh key, and may read unreliably due
to proto1 silego reset circuit.
2) Lightbar may not start in the correct state.
3) EC 'hibernate' command will not work.
4) Board version may read incorrectly.
BUG=chrome-os-partner:9661
TEST=manual
1) powerbtn -> system powers on, lightbar displays proper sequence
2) version -> board version 1 (EVT)
3) power+refresh+esc -> system boots into recovery mode
4) power+refresh, then power button -> system reboots, then boots normally
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I699946e365d15ae38622b69da1a0241e72d05f61
Reviewed-on: https://gerrit.chromium.org/gerrit/26053
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
A host command to set fan duty cycle is recently added and mock PWM
module doesn't provide the implementation. This breaks our unit test.
Let's fix this.
BUG=chrome-os-partner:10820
TEST='thermal' unit test passed.
Change-Id: I8644742cfec7d2112d7ff1e266b5ac3429c46945
Reviewed-on: https://gerrit.chromium.org/gerrit/26019
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
This forces the fan PWM duty cycle to a fixed percentage (0-100). It's only
used for airflow testing.
BUG=chrome-os-partner:10747
TEST=manual
Using this ectool, try
ectool fanduty 0
ectool pwmgetfanrpm
ectool fanduty 50
ectool pwmgetfanrpm
ectool fanduty 100
ectool pwmgetfanrpm
You should see (and hear) the fan speed up. If you have an EC console, you
can run
faninfo
and it should show that the 'Target:' is unrelated to the 'Actual:' value.
Change-Id: Iac332fb3ba63f96726cf7f64061b3ce22d2e76fd
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25965
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the EC shares the I2C-2 bus with the battery and the charger, we
don't want to be a master on that bus when the AP is ON and can send us
I2C messages.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
TEST=on Lucas DVT, check we can read battery info when AP is OFF and we
cannot when AP is ON.
Change-Id: I920a10ae9eff31bd00e4d3a5aec19d6f03b65a33
Reviewed-on: https://gerrit.chromium.org/gerrit/25959
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10747
TEST=manual
Boot the CPU (the fan is off otherwise). From the EC console run
faninfo
It should show the fan duty cycle changing to maintain a specific RPM.
Run
fanduty 50
faninfo
Now the fan duty cycle should be fixed around 50%.
Change-Id: I13e4b0a7e5b2661769d64bf93342483d0419545d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25900
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The flash commands syntax has slightly evolved
and the watchdog needs to be switched off even though we are doing a
reset halt.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:7420
TEST=flash Link EC using OpenOCD inside the chroot:
sudo USE="ftdi" emerge openocd
sudo openocd -f chip/lm4/servo_v2.cfg
flash_link
Change-Id: Ieef5df682a945646525267a7b702e953796f3f00
Reviewed-on: https://gerrit.chromium.org/gerrit/25561
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Rather than just reset with no information when we hit a watchdog, try
to anticipate the problem and display a trace message as on lm4.
This solution is not ideal since we must constantly reset the WWDG to make
it work. It may be better to look at dedicating a timer to this purpose
instead, since we are really just shadowing the IWDG and don't actually
need the reset functionality.
One problem is that we now have a fairly short time limit on many
operations, since if we can't service an interrupt within about 30ms then
the WWDG will reset the system.
It also affects JTAG since it seems that the watchdog goes off the first
time JTAG is invoked to program the flash. The solution here is to retry.
For these reasons it is implemented as an option, CONFIG_WATCHDOG_HELP.
BUG=chrome-os-partner:10145
TEST=manual:
build for all boards
On snow:
> waitms 500
See that there is no message
> waitms 1300
Time: 0x0000000000733ba3 us
Deadline: 0x00000000006b6db2 -> -0.511473 s from now
Active timers:
Task Ready Name Events Time (s)
0 R << idle >> 00000000 0.000000
1 R WATCHDOG 80000000 0.000000
2 KEYSCAN 00000000 0.000000
3 GAIAPOWER 00000000 0.000000
4 R CONSOLE 00000000 0.000000
5 HOSTCMD 00000000 0.000000
--- UART initialized after reboot ---
[Reset cause: watchdog]
[Image: RO, snow_v1.1.32-8c00326-dirty 2012-06-03 07:54:29 sjg@sglass.mtv.corp.google.com]
done
Change-Id: I042fcc9ecd9c21210ea3826ca69c943aab949d1f
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24398
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We want this function to be available for all chips, so move it into a
generic place.
The task_disable_irq() from the LM4 version can be left in
watchdog_check(), to keep the watchdog_trace() function generic.
BUG=chrome-os-partner:10145
TEST=build for all boards
Change-Id: I98c60ce5958f1498b84a233ef04290a68a7838c5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24397
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The SCB registers are defined in the ARMv7-M architecture, so they are
common to all chips.
We will need System Control Register (SCR aka SYSCTRL) to implement
power management on stm32.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=snow
Change-Id: I35c283731306541b3d21398c96fdca89954fe20a
Reviewed-on: https://gerrit.chromium.org/gerrit/25392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Note that util/comm-lpc.c already does this for the host side of the
commnunication.
BUG=chrome-os-partner:10444
TEST=none; all EC responses are currently well-formed
(but do try 'ectool hello' from host and make sure it still works)
Change-Id: I731ed326e281be6a7435edfa03c783225e105b72
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25124
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Previously, the host could write to this space and corrupt the memmap data.
BUG=chrome-os-partner:10210
TEST=manual
From a root shell:
localhost ~ # io_read32 0x960
0x574e5553
localhost ~ # io_write32 0x960 0x1234
localhost ~ # io_read32 0x960
0x574e5553
That verifies that the EC is rejecting host writes on the memmap range
localhost ~ # ectool hello
EC says hello!
That verifies the host is still able to write to the user param range
Change-Id: I8c29571f439a14f308ed73f4c641264e17f944e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25115
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
