Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Group temperature sensors into different types so we only have to set
temperature threshold for each type instead of each sensor.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Fan control still works.
Change-Id: I7acc714c32f282cec490b9e02d402ab91a53becf
Modify thermal engine to treat temperature threshold as a 3-degree range
instead of a certain value. This way the fan do not keep turning on and
off, while the temperature floating around the threshold value.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Set threshold to current temperature. The fan turns on and does not
immediately turns off.
Change-Id: Iad1de05a409dbbc573a8ffd0ece0dc7961b20806
Update test python scripts for recent trace modifications :
- lack of firmware B
- updated motd
Update QEMU to deal gracefully with various new registers accesses.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: I59a53822193b7377fe5f61f75c951b6cd24fc54b
Allow to build without the power button task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: Ibc757a6641f195f0d10e6a673792b996694f8cec
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Keyboard reset now triggers a cold reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then do 'x86reset cold' for a cold reset or
'x86reset warm' for a warm reset. Check x86 debug console to see that
coreboot detects the warm (soft) reset.
Change-Id: I00930d9f5df98365277cd5c7f2eb8f135c4e4398
The re-scheduling is protected by increasing our priority to -1,
according to ARMv-M architecture manual, we need an ISB after setting
the faultmask register to ensure that the new priority is visible.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8492
TEST=run on proto-0.5 and see that the temperature sensor and battery
tasks are longer hanging (see the bug for details how to check it)
Change-Id: Ia55859cf5c9101a09c61be7647a920126fc0a3b9
When updating the lock field of the mutex to acquire it, if the store
exclusive fails, we want to retry immediatly else if the failure has
been triggered by the other user doing the mutex_unlock we might not be
woken up.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8492
TEST=run on proto-0.5 and see that the temperature sensor and battery
tasks are longer hanging (see the bug for details how to check it)
Change-Id: I0c8a4e997666a7781b3837f0dbbc47ffbc06b6c3
Until we solve the I2C hanging issue, we need a reliable way to read
temperature. Add back LPC temperature read command that actually trigger
a I2C read.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8452,chrome-os-partner:8495
TEST=none
Change-Id: Icddd1fe3c1f09889bca633af19041a8aca582de9
Currently temperature polling task sometimes hangs. Until we solve this
problem, fan should not be turned off according to temperature readings.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8479
TEST=none
Change-Id: I3892c55dd18d3533515d5537b1a877e4fc36d631
Make temp sensor report 0xfd when sensor is unpowered.
Also refactor power specification of temp sensors from thermal.c to
temp_sensor.c.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8279
TEST=none
Change-Id: Ib13813bdbac2f048fbc3b98fae5bbf104ebf37d7
To handle outp(0x64, 0xfe) instruction from host.
BUG=chrome-os-partner:8464,chrome-os-partner:8397
TEST= build on bds and l*. tested on proto 0.5.
Change-Id: I8cb3a870b2a5c7a711dc911ba44e154813e9f123
Remove dummy boot-time output to UART1; no longer needed now that
there's a debug command to do the same thing.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
comxtest - prints default message to x86 UART
comxtext ccc123 - prints 'ccc123' to x86 UART
Change-Id: I37d37aeca06bf71b106f5ad3473a79780fd089a9
Not compiled into any target; new version of temp_sensor.c is in common/
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=build link and bds
Change-Id: I00232a7cd8a8a9ee6353c5f04c86fcacc83cbd3e
For debugging PCH reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then use x86reset to reset it. Should see line state changes printed.
Change-Id: Ief2f09bd0986339812183d0b32dc0208437d1103
Jumping (currently rebooting, see crosbug.com/p/8100) to the RW image should
be done by vboot_init(), not vboot_pre_init().
As currently written, vboot_init() has to come AFTER these function calls:
task_init(); // sets up interrupts so that uart will work
watchdog_init(1100); // in case we fall over somewhere
uart_init(); // we'd REALLY like to see some debugging output
system_init(); // may go away with crosbug.com/p/8100
keyboard_scan_init(); // check for F3 to go to recovery mode
flash_init(); // maybe set RO regions (this should come earlier!)
eeprom_init(); // this is where the try_b flags are kept
BUG=chrome-os-partner:7459
TEST=none
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I0ec3f6bcc26a308bb1005a944990963853b88b60
Make thermal engine trigger SMI on overheating and sensor failure.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8249
TEST=none
Change-Id: I1f8c1d05ae69fae4736c4cc92b060b1813007249
(new method, and x86reset command to call it)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8460
TEST=manual: powerbtn, wait for system to boot, x86reset
Change-Id: Iad3f5c268b334e8d0ec1adfa2878f9e9d5927b9f
Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
Note that this is a big security hole and should be removed after we
complete the EC autoupdate mechanism and vboot code.
To full update EC firmware on proto 1.0, we need a manual way to switch
EC running on RO/RW. This CL implements the LPC command.
BUG=chrome-os-partner:8415
TEST=on proto 0.5.
ectool reboot_ec RW_A # EC boots to RW A
ectool reboot_ec RO # EC boots to RO
Change-Id: Ibf050328bc4e3d2c6d72bfc478d6334f11f0eb46
And faninfo now checks if the fan is powered.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
1) faninfo --> fan is initially disabled and powered off
3) gpioset enable_vs 1 --> fan is now powered on, but still disabled
2) fanset 8000 --> fan is now enabled, and you should hear it
Change-Id: I97f35a20022cabd4520522f2d18ecb7603faabd1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
This CL adds LPC commands to provide the following information:
- Design Capacity (dword)
- Last Full Charge Capacity (dword)
- Design Voltage (dword)
- Design Capacity of Warning (dword)
- Design Capacity of Low (dword)
- Battery Type (ascii)
- Model Number (ascii)
- Serial Number (ascii)
- OEM (usually Vendor) (ascii)
- Battery charge cycle count (dword)
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8181
TEST=none
CQ-DEPEND:Iad4d63c996272568b5a661a6716790ef151b29c5
Change-Id: Iabaf7d9862e15c5b21cf5170cf43450e472b7836
These bits are as per definition in "Chrome EC LPC Communication"
document.
BUG=chrome-os-partner:8351
TEST=manual
. tested in concert with coreboot modifications introducing the EC
command implementation
Change-Id: I46d5795e06854e34584132c7fdb37e29150ce179
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
The STM32L15xx monitor does not implement the mass erase,
so we need to use the page erase feature and loop.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery, fill the flash with a pattern, then erase, write a
firmware image, read back the content of the flash, run the firmware.
Change-Id: Icf0e9812a5d491fea78472a0203ddbbc3e813b2f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8350
TEST=manual
Hack a task function to return. Then see that it prints an error to
the debug console and the EC continues running, instead of seeing a
hard-fault.
Change-Id: Iacd2b83c4d4845bb8e6c61e07c3150df8edc7e49
Also prints the current timer value when inits are done, and when the
watchdog task first gets to run (after all higher priority tasks sleep
at least once).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I342f86ad087fd18ab064a10a5bcdd0b69ee373d0
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8321
TEST=manual:
type 'battery' in EC serial console, check following fields:
Manufacturer
Device name
Device chemistry
CQ-DEPEND:I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Change-Id: Iad4d63c996272568b5a661a6716790ef151b29c5
Implement a generalized I2C transmit-receive function that
write-then-read blocks of raw data. Original 8-bit and 16-bit
read/write functions are refactored.
SMBus read-block protocol for ASCII string is also implemented
based on this API.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8026,8316
TEST=manual:
Type 'lightsaber' to check 8-bit read/write.
Type 'charger' to check 16-bit read.
Type 'charger input 4032' to check 16-bit write.
Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Note that this only handles lid and power button; see
crosbug.com/p/8325 for write protect.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8185
TEST=manual
1. Check state with lid open
localhost ~ # ectool switches
Current switches: 0x01
Lid switch: OPEN
Power button: UP
Write protect: ENABLED
2. Press power button
localhost ~ # ectool switches
Current switches: 0x03
Lid switch: OPEN
Power button: DOWN
Write protect: ENABLED
3. Release power button and close lid
localhost ~ # ectool switches
Current switches: 0x00
Lid switch: CLOSED
Power button: UP
Write protect: ENABLED
Change-Id: I25f2fa3dfeac004dde9b10a4243ee235875f1b6e
Useful when debugging to determine if a user has an official build or
not, particularly early in the devel process where we're handing
builds to everyone. Particularly useful for proto1, since not all
those systems will be case-open servo-attached.
Also move get-version LPC command into system.c, where it's closer to
the system functions it calls (matches what we do for other host
commands).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Idb0f6edf31ca00e32f083be0b0d3f23ab79c5fba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8324
TEST=manual
1. When system is off, open lid. Debug console should show PB PCH pwrbtn activity.
2. Wait for system to boot.
3. Quickly close and open lid. Debug console should not show pwrbtn activity.
Change-Id: Ia018ff06a31ac2a68f20021d17e47ddb06096eb8
...since x86_power_in_S0() is a terrible function to have implemented
for gaia chipsets, and I need to add more detectable states for lid
switch handling anyway.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I0c90c6875b27d1bf23f093e88e34eabf2a8c86e4
(Also define other host events)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8308
TEST=manual:
Use magnet to trigger lid-closed and lid-open.
'hostevent' should show raw events = 0x3.
Press power button.
'hostevent' should now show raw events = 0x7.
Change-Id: I9c8367d5152d526299a7a3149250de84cc2e0557
