BUG=chromium:769895
BRANCH=servo
TEST=On servo_v4, attach OEM Apple charger to power port and verify
negotiation to 9V and port / ILIM selection from charge_manager. Attach
samus to DUT port and verify 9V charging.
Change-Id: Icf16f6e8c99af4fbb48a83b7a36f550c20f5fd69
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/713944
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On Scarlet rev2, we see rt9467 has trouble
detecting VBUS level reliably.
Let's use TCPC to detect VBUS instead as we once
considered in b:65698085.
BUG=b:65698085, b:67917615
BRANCH=none
TEST=verify usb mouse and charging works through usb-c hub
Change-Id: I439cd3267bb26d5cdcbfd4a3c48179cf7942b870
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/725000
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch is to enable fan through PWM4 output and TACH feedback
from TA2 GPIOA6, and move EC_PLATFORM_RST to GPIO45.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz chromeos-ec and use fanduty and faninfo from EC
console to control and check fan status. Probed oscilloscope
on PWM output and checked the duty as expected. Made sure the
fan was stopped when DUT entered S3 and was running when DUT
resumed from S3.
Change-Id: I09f3ac43d2e4170b2aff3830f832bc5fd46a15c0
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/627542
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The GPIO lines for the charger LED are being used as simple on/off and
no PWM control is used. Removed them from the pwm channel list so that
it reflects more accurately what PWM is used for on Coral.
BUG=b:64192049
BRANCH=None
TEST=make -j BOARD=coral
Change-Id: I3546001f96cb01f81fa1c373de28e460b63012c1
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/717187
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Robo devices have a power button LED. For these devices the desried
power button LED behavior is:
S0 -> always on
S3 -> charging, then 500 mSec off, 3 seconds on
S3 -> not charging, always off
S5 -> always off
Because the hook tick runs at 200 msec, using 600 msec for the off
period when blinking in S3.
BUG=b:64015212
BRANCH=None
TEST=Manual
This LED is not connected on EVT, so added a wire on GPIO02 and used a
scope. Verifed that in S0 the signal level is low, and in S3 that it
control signal toggles 600 mSec high/3 sec low. Verifed than in S5
control signal is high.
Change-Id: I72438a009a507fcddaae5a673bf3bc83988f2dd5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/717183
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This reverts commit df12bc1c02.
Reason for revert: the config flag is deprecated and should not use in any project.
Original change's description:
> hana: disable console input when system is locked
>
> Shipped devices were found that batteries could enter ship mode
> unexpectedly. Fail rate is about 5/700pcs per day. Failure happens
> when battery is charged fully and eneters sleep(mem), and then AC is
> plugged out.
> Battery ship mode is entered because ec execute console command
> "cutoff". Still do not know what causes that when no any device
> connected to servo board connector (console TX and RX are floated).
> Enable this config item will cut off route from RX input and fix
> the issue.
>
> BUG=b:67033247
> BRANCH=none
> TEST=with 50 DUTs, flash ec to DUTs and then lock the system, charge
> the battery from about 80% capacity to 100% capacity, close the lid
> for 20 minutes, unplug AC, boot the system, all DUTs boot, no DUT's
> battery enter ship mode. The same test repeats 3 times.
>
> Change-Id: I9939fed1467026bc2d85c645b6ecebae4b6796c6
> Signed-off-by: Chao Ge <chao.ge@bitland.com.cn>
> Reviewed-on: https://chromium-review.googlesource.com/693921
> Commit-Ready: ge chao <chao.ge@bitland.com.cn>
> Tested-by: ge chao <chao.ge@bitland.com.cn>
> Reviewed-by: Rong Chang <rongchang@chromium.org>
Bug: b:67033247
Change-Id: Ide8a3cc8d1eeee9914922d47ec12c44b7d0e9675
Reviewed-on: https://chromium-review.googlesource.com/718237
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
No Coral configurations will contain the ambient light sensor
(ALS). Therefore, no reason to have support for this in the board.c/.h
files.
BUG=b:38271876
BRANCH=eve
TEST=make -j BOARD=coral and verify no errors.
Change-Id: Ib8f6c546d5fb4d0bb8d37e84a62c4725e37be6f5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/711196
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This CL adds the config option CONFIG_DYNAMIC_MOTION_SENSOR_COUNT and
SKU table which contains the form factor for all known SKUs. Once the
SKU ID is known, the variable motion_sensor_count is set based on
CLAMSHELL or CONVERTIBLE designation in the SKU table. If there isn't
a matching SKU ID in the table then motion_sensor_count will be
initialized to the ARRAY_LENGTH of motion_sensors.
BUG=b:38271876
BRANCH=None
TEST=Manual
Tested with Robo360 (SKU ID 71) and verified the motion sensor count
and that the motion senors were initialized in the EC console log.
[0.088188 Motion Sensor Init: count = 3]
[0.346097 Lid Accel: MS Done Init type:0x0 range:2]
[0.370386 Base Accel: MS Done Init type:0x0 range:2]
[0.386790 Base Gyro: MS Done Init type:0x1 range:1000]
Tested with Santa EVT (SKU ID 3) and verified motion_sensor_count is 0 and
no EC console messages showing sensor initialization failures.
Change-Id: Ia3d60f8c8dd4435dd7cfb80a860f809de2fb931e
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/711195
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fizz allocates 15W to the type-c port. This patch allows the port
to use it.
BUG=b:67682343
BRANCH=none
TEST=Verify 5V 3A PDO is offered.
Change-Id: I1560c0c7cb04379f5e4c9893753afe4a7f0cefe4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/713583
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Shipped devices were found that batteries could enter ship mode
unexpectedly. Fail rate is about 5/700pcs per day. Failure happens
when battery is charged fully and eneters sleep(mem), and then AC is
plugged out.
Battery ship mode is entered because ec execute console command
"cutoff". Still do not know what causes that when no any device
connected to servo board connector (console TX and RX are floated).
Enable this config item will cut off route from RX input and fix
the issue.
BUG=b:67033247
BRANCH=none
TEST=with 50 DUTs, flash ec to DUTs and then lock the system, charge
the battery from about 80% capacity to 100% capacity, close the lid
for 20 minutes, unplug AC, boot the system, all DUTs boot, no DUT's
battery enter ship mode. The same test repeats 3 times.
Change-Id: I9939fed1467026bc2d85c645b6ecebae4b6796c6
Signed-off-by: Chao Ge <chao.ge@bitland.com.cn>
Reviewed-on: https://chromium-review.googlesource.com/693921
Commit-Ready: ge chao <chao.ge@bitland.com.cn>
Tested-by: ge chao <chao.ge@bitland.com.cn>
Reviewed-by: Rong Chang <rongchang@chromium.org>
The Nasher simplo battery uses the Reneas fuel gauge. The table entry
for this battery had TI fuel gauge assumption. This CL modifies the FET
info to use register 0x43 and bits 1|0.
In addition added console log entry for the FET register, mask, and
expected value. In normal cases this log message will appear only
once, but when recovering from battery cutoff, will have have one
entry per call until the battery is no reporting as disconnected.
BUG=b:64887361
BRANCH=None
TEST=Using nasher proto system connected the SMP-SDI3.72
battery. Tested normal start up and after doing a battery cutoff.
Normal caseL:
[0.038624 found batt:SMP-SDI3.72}
[0.046017 SW 0x01]
[0.068892 hash start 0x00040000 0x00020d08]
[0.075775 Battery FET: reg 0x001b mask 0x0003 disc 0x0000]
After battery cutoff:
[0.146889 Battery FET: reg 0x0008 mask 0x0003 disc 0x0000]
[0.161523 Battery FET: reg 0x0008 mask 0x0003 disc 0x0000]
.
.
[0.476275 Battery FET: reg 0x001b mask 0x0003 disc 0x0000]
Change-Id: Ie378e9a795f543763a02c6c062235b265be0f71c
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/705260
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Implemented an led state table based implementation for LED control of
the battery LED. The states are the same as previous Coral/Reef single
LED control with the exception of allowing for 3 charging states based
on the current battery state of charge level. Now the desired state
is determined and that's used to access the correct LED behavior based
on the current tick count.
Changed from a one second tick to the NPCX 200 msec tick so the Robo
power button pattern can be supported as well.
The are currently two tables implemented, one for Robo devices, and
the default table. At init time, after the SKU ID is determined, the
correct table is assigned.
BUG=b:64192049
BRANCH=None
TEST=Manual
Tested both Coral proto and Robo EVT systems. Verifed operation in the
different states. During tested used modified charging level tables
so the 3 different charging states could be exercised. Also removed
battery to verify the error state.
Change-Id: Ifc6935f73d4fed1eeec9c5aab13f6346f61857ff
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/693387
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The decision on whether to ramp (and how high) depends on the quirks of
charger identification, so move the decision out of board, into the
drivers that implement usb_charger.
Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better
contrast with the existing CONFIG_CHARGE_RAMP_HW.
BUG=None
TEST=Manual on kevin, verify ramp occurs when port plugged into Z840
workstation.
BRANCH=None
Change-Id: I5b395274133837a18a4f4ac34b59b623287be175
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/702681
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a PERSO_AUTH appid to sign data passed through the
AUTH mn50.
Add a signer command to start and generate signatures.
Clean UART init to avoid spurious nonprinting characters
that will contaminate the siugnature.
BUG=b:36910757
BRANCH=None
TEST=generates signature for uart and spi
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I5fc3c4ee34898421060b57b774a09734f6a1bae5
Reviewed-on: https://chromium-review.googlesource.com/670984
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Turn on FORCE_CONSOLE_RESUME and also shuffle around
the context to ensure alphabetical order.
BUG=b:67379662
BRANCH=none
TEST=manually on Scarlet rev1: put AP in suspend mode,
verify EC console still works, and confirm EC goes into
low power idle mode by EC console command 'idlestats'.
Change-Id: I2563e6ed4fdb47123912932ad8ba9172b0c9c13c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/702918
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Boards that use charge_manager have identical implementations of
typec_set_input_current_limit() and pd_set_input_current_limit(), so
move these functions to charge_manager.
BUG=b:67413505
TEST=`make buildall -j`, also verify that fizz continues to power-on and
boot AP, in both protected and unprotected mode, with barrel jack power
and with zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I99a5314d02c4696db944c0f8ac689405f4f1f707
Reviewed-on: https://chromium-review.googlesource.com/701412
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
CONFIG_CASE_CLOSED_DEBUG (CCD functionality implemented by EC) is no
longer used in conjunction with CONFIG_USB_POWER_DELIVERY, and the
common routines are only used by one board.
BUG=chromium:737755
BRANCH=None
TEST=`make buildall -j`
Change-Id: Idc3d2fccef6cbec2af786cef634d752a02a0e859
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656315
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This enables pull-down on F_DIO1 (SPI MISO), and F_DIO0 (SPI MOSI),
whenever the EC is not doing SPI flash transactions. This avoids
floating SPI buffer input (MISO), which causes power leakage.
BRANCH=none
BUG=b:64797021
TEST=Flash soraka, check output of rw .b 0x400C3029 is 0x80
Check that U58 (SN74LVC244ARWPR) leakage drops from 1.2 mA to 0.
TEST=1. flashrom from host to EC spi flash using servo
2. flashrom from host to EC spi flash using suzyq
3. flashrom from device to EC spi flash
4. EC SW sync
Change-Id: I5ac22142f6a1a5b1c31d6ae272ed7516a112f29e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/701717
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This patch undefines CONFIG_SYSTEM_UNLOCKED, which forces the system
to be unlocked, and defines CONFIG_USB_PD_COMM_LOCKED, which enables
PD only if EC is in RW. With this change, if SW write-protect is
enabled, the system will stay in G3 until 50W or more power is
supplied.
BUG=b:38462249
BRANCH=none
TEST=Lock Fizz and boot it on type-c adapter. Verify RW image is
successfully verified and executed.
Change-Id: Id8255c5c8e6af93bda3fd4de079008561f46e14c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/558377
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A couple of bugs have crept in with the latest series of patches:
- the board ID value endianness does not have to be changed
- the test RMA server public key value is wrong
BRANCH=cr50
BUG=b:67007905
TEST=the generated challenge is now accepted by the server, and the
generated auth code matches between the server and the Cr50.
Change-Id: I18f413ab0bcc14d9cc50b115ac3784fdfcd5851c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/700798
Reviewed-by: Michael Tang <ntang@chromium.org>
Runtime S0ix results in SLP_S0 signal being toggled continuously
resulting in an interrupt storm on the EC. In order to avoid this,
enable SLP_S0 power signal only when host indicates intent to enter
S0ix and disable when host exits from S0ix.
BUG=b:65421825
BRANCH=None
TEST=Verified that runtime S0ix no longer results in interrupt storm
on EC. Normal S0ix works fine on soraka. Verified state of SLP_S0
using powerindebug.
Change-Id: I9ca62b8122afd8acedc2c353106407fdcc284925
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the battery gets to returns the FULL flag, bd99956 charging is
disabled and battery learning is enabled. This state will remain until
the FULL flag is cleared by the battery. The original fix had this
level at 97%, but on the various batteries tested this appears to
happen at 95%. The CONFIG_BATTERY_LEVEL_NEAR_FULL allows an adjustment
for this level and is only used for LED states.
BUG=b:64192049
BRANCH=None
TEST=Manual Let system charge to 100% when FULL flag is set in the
battery, verified the LED was in correct state. Then let battery drain
until the FULL flag is clear and observe that the battery requests
charge current. The LED stays in the expected full charge state.
Change-Id: I74d26abd5d8021bcfacdc3a4c3d4baba6a978bca
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/693386
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable necessary flags for the Cr50 to start supporting RMA
authentication. This also requires that the RMA server public key
definition is split between the actual and test. Even though they are
the same at this time, the actual public key would be defined in the
new future and it would be different from the test key.
BRANCH=cr50
BUG=b:65253310
TEST=make buildall -j passes. More tests were conducted on the full
patchset.
Change-Id: I5a3f9d8c71374d78192e3f0a2752391b842da962
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/691554
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To aid with severe flash space shortage, let's enable
CRYPTO_TEST_SETUP only if CR50_DEV is set to a value exceeding 1.
board/mn50/board.h used to define CR50_DEV without any value assigned
to it, correct this so that the check in dcrypto.h works when mn50 is
built.
BRANCH=cr50
BUG=b:65253310
TEST=compiling with CR50-DEV=1 vs CR50_DEV=2 saves more than
17.5 Kbytes per RW image.
Change-Id: Ic77fa45b1a8f7631efa91c08e63438d412196eed
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/690993
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, when CCD is opened, there is no way to disable the EC
and/or AP UARTs. But if there is some problem with the EC and/or AP,
and their UARTs are spamming interrupts, it can make debugging more
difficult.
If servo detection malfunctions, then CCD may drive the ports and
interfere with servo.
Add a new ccdblock command to disable the AP UART, EC UART, or any
ports shared with servo, until the next cr50 reboot.
BUG=b:65639347
BRANCH=cr50
TEST=manual with CR50_DEV=1 image, AP/EC powered on, suzyq connected
ccdblock --> (none)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
ccdblock AP on
ccdstate --> UARTEC+TX I2C SPI
ccdblock EC on
ccdstate --> I2C SPI
ccdblock -> AP EC
ccdblock AP off
ccdstate --> UARTAP+TX I2C SPI
ccdblock EC off --> (none)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
ccdblock SERVO on
ccdstate --> UARTAP UARTEC
ccd lock
ccdblock AP on --> access denied
Change-Id: I3dcc8314fc98a17af57f2fe0d150ecd1a19ccf52
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/693041
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
On proto3, PMIC isn't powered on POR, thus board_pmic_init fails.
With this change, EC waits until AP power is ready before it
notifies HOOK_CHIPSET_PRE_INIT where PMIC will be initialized.
When AP power is ready, PMIC should be ready as well.
BUG=b:65839247,b:64944394
BRANCH=none
TEST=Run reboot [/cold/ap-off] command on BJ and Type-C.
Change-Id: I7e7e07b5acf92167584966ded0a5f14fb6b04f0b
Reviewed-on: https://chromium-review.googlesource.com/672152
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fizz EC verifies RW by itself and jumps to RW before AP boots.
If this fails, the system needs recovery. Since EC isn't
capable of showing any info on a display, we use the power
LED to inform the user.
BUG=b:66914368
BRANCH=none
TEST=Make Fizz fail RW verification. Observe LED illuminates
in red.
Change-Id: Ia07de60a316b40e74b1917903996d78750b4ae43
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/683218
This patch makes the LED blink to alert the user when there is
not enough power to boot the system.
This patch also changes minimum boot power to 50W. It's common
for all SKUs.
BUG=b:37646390
BRANCH=none
TEST=Power Fizz with 15W, 45W, 60W chargers. Verify LED blinks as
expected.
Change-Id: If269897f5022f6cba80f37ce03e2315cfb2cf504
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/682876
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to response EC ACPI device orientation command or
keyboard/trackpad didn't work on OS image version R58 and
after.
BRANCH=none
BUG=none
TEST=keyboard and trackpad work on R58 and after.
Change-Id: I49f9c90e73a5e529eb228169e4148f4dcd4a45e6
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/689715
Reviewed-by: Shawn N <shawnn@chromium.org>
The current stm32 rtc driver only uses RTC_TR and RTC_SSR.
So we son't be able to use rtc for applications which need
time > 24 hours.
To support such applications, this patch adds operations
for RTC date register (RTC_DR).
BUG=b:63908519
CQ-DEPEND=CL:666985
BRANCH=none
TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0',
verify the conversion between calendar time and Unix epoch time works.
Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/659337
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
1.Add LG battery for Santa and Porbeagle.
2.Santa LG battery manufacture name is same as BATTERY_LGC011, so use
device name to recoginze Santa LG battery.
3.These two battery have different process to get FET status, make
sure battery not use this process is before BATTERY_LGC15 to separate
these two different process.
BRANCH=none
BUG=b:65426428, b:64772598
TEST=Make sure battery can cutoff by console "cutoff" or "ectool cutoff"
and resume by plug in adapter.
Change-Id: I7095b9d0915fb4d39aa6c9f8c8751aa22941e938
Signed-off-by: David Huang <David.Huang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/674472
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch raises the max power for a type-c adapter to 60W (20V @3A).
We can't go above the regular cable capacity (3A) until we add e-marked
cable detection.
BUG=none
BRANCH=none
TEST=Boot Proto3 on Zinger. Observe 60W (20V @3A) is selected.
Change-Id: I9670d710e363c7db1136a7ce7a7f8401b0ad8240
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679210
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In this CL, we add the follow changes for npcx7 evb board:
1. Add comments in the build.mk to indicate how to set
CHIP_VARIANT for EVBs which use different npcx7 ec.
- npcx7m6f : 144 pins (default)
- npcx7m6g : 128 pins
2. Turn on the eSPI host interface as default in board.h
BRANCH=none
BUG=none
TEST=No build errors for "make buildall".
Change-Id: Ib926e8596a09a28f547c35a0256be2aa394f9a36
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/674887
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The hash test code memory management is somewhat loose: it does not
clean up allocated buffer, but then uses it to check for presence of
the previously created handles, which can result in false positives.
Let's zero the buffer each time it is allocated and let's use
hash_test_db.contexts as the indicator if the buffer is allocated or
not.
BRANCH=cr50
BUG=none
TEST=ran ./test/tpm_test/tpmtest.py, observed rsa tests pass.
Change-Id: Iad4b4e2662fc7266ee6f556f6ddfd0051e7172d7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665321
Reviewed-by: Shawn N <shawnn@chromium.org>
