This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Image used size is now part of the image_data struct present in all
images at a fixed offset, so use it rather than scanning from the end of
the image.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns
the same value as the old implementation, for both RO and RW images.
BRANCH=None
Change-Id: I35f0aa87f5ab1371dbd8b132f22b9d0044358223
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450859
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450858
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
All boards have been transitioned to charge_state_v2.c
So charge_state_v1.c, HOOK_CHARGE_STATE_CHANGE, and
CONFIG_CHARGER_TIMEOUT_HOURS can be removed
BUG=chrome-os-partner:36272
TEST=make -j buildall
BRANCH=none
Change-Id: I3f20c5198ea75185f9894deb792575a1be31432a
Reviewed-on: https://chromium-review.googlesource.com/435467
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Image used size is now part of the image_data struct present in all
images at a fixed offset, so use it rather than scanning from the end of
the image.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns
the same value as the old implementation, for both RO and RW images.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic8db5c706d82f7ca2ded2e90129747e7fbefdb38
Reviewed-on: https://chromium-review.googlesource.com/427959
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I49ea5fc27a7f11f66daba485a87d0dfe7d0c770f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/427408
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chromium:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
BOARD with host commands and private host commands
0004d0ec R __hcmds
0004d0ec R __host_cmd_0x00000x0000
0004d0f8 R __host_cmd_0x00000x0001
0004d104 R __host_cmd_0x00000x0002
0004d110 R __host_cmd_0x00000x0003
0004d11c R __host_cmd_0x00000x0004
0004d128 R __host_cmd_0x00000x0005
0004d134 R __host_cmd_0x00000x0007
0004d140 R __host_cmd_0x00000x0008
0004d14c R __host_cmd_0x00000x000a
0004d158 R __host_cmd_0x00000x000d
0004d164 R __host_cmd_0x00000x0010
0004d170 R __host_cmd_0x00000x0011
0004d17c R __host_cmd_0x00000x0012
0004d188 R __host_cmd_0x00000x0013
0004d194 R __host_cmd_0x00000x0015
0004d1a0 R __host_cmd_0x00000x0016
0004d1ac R __host_cmd_0x00000x0017
0004d1b8 R __host_cmd_0x00000x0087
0004d1c4 R __host_cmd_0x00000x008c
0004d1d0 R __host_cmd_0x00000x008f
0004d1dc R __host_cmd_0x00000x0092
0004d1e8 R __host_cmd_0x00000x0093
0004d1f4 R __host_cmd_0x00000x0097
0004d200 R __host_cmd_0x00000x0098
0004d20c R __host_cmd_0x00000x00b6
0004d218 R __host_cmd_0x00000x00d2
0004d224 R __host_cmd_0x00000x00d3
0004d230 R __host_cmd_0x3E000x0000
0004d23c R __host_cmd_0x3E000x0002
0004d248 R __evt_src_EC_MKBP_EVENT_HOST_EVENT
0004d248 R __hcmds_end
BOARD with host commands only
100bc888 R __hcmds
100bc888 R __host_cmd_0x00000x0000
100bc894 R __host_cmd_0x00000x0001
100bc8a0 R __host_cmd_0x00000x0002
100bc8ac R __host_cmd_0x00000x0003
100bc8b8 R __host_cmd_0x00000x0004
100bc8c4 R __host_cmd_0x00000x0005
100bc8d0 R __host_cmd_0x00000x0006
100bc8dc R __host_cmd_0x00000x0007
100bc8e8 R __host_cmd_0x00000x0008
100bc8f4 R __host_cmd_0x00000x0009
100bc900 R __host_cmd_0x00000x000a
100bc90c R __host_cmd_0x00000x000b
100bc918 R __host_cmd_0x00000x000d
100bc924 R __host_cmd_0x00000x0010
100bc930 R __host_cmd_0x00000x0011
100bc93c R __host_cmd_0x00000x0012
100bc948 R __host_cmd_0x00000x0013
100bc954 R __host_cmd_0x00000x0015
100bc960 R __host_cmd_0x00000x0016
100bc96c R __host_cmd_0x00000x0017
100bc978 R __host_cmd_0x00000x0025
100bc984 R __host_cmd_0x00000x0026
100bc990 R __host_cmd_0x00000x0029
100bc99c R __host_cmd_0x00000x002a
100bc9a8 R __host_cmd_0x00000x002b
100bc9b4 R __host_cmd_0x00000x002c
100bc9c0 R __host_cmd_0x00000x0044
100bc9cc R __host_cmd_0x00000x0045
100bc9d8 R __host_cmd_0x00000x0046
100bc9e4 R __host_cmd_0x00000x0047
100bc9f0 R __host_cmd_0x00000x0061
100bc9fc R __host_cmd_0x00000x0062
100bca08 R __host_cmd_0x00000x0064
100bca14 R __host_cmd_0x00000x0065
100bca20 R __host_cmd_0x00000x0067
100bca2c R __host_cmd_0x00000x0087
100bca38 R __host_cmd_0x00000x008c
100bca44 R __host_cmd_0x00000x008d
100bca50 R __host_cmd_0x00000x008f
100bca5c R __host_cmd_0x00000x0092
100bca68 R __host_cmd_0x00000x0093
100bca74 R __host_cmd_0x00000x0096
100bca80 R __host_cmd_0x00000x0097
100bca8c R __host_cmd_0x00000x0098
100bca98 R __host_cmd_0x00000x0099
100bcaa4 R __host_cmd_0x00000x009e
100bcab0 R __host_cmd_0x00000x00a0
100bcabc R __host_cmd_0x00000x00a1
100bcac8 R __host_cmd_0x00000x00a8
100bcad4 R __host_cmd_0x00000x00a9
100bcae0 R __host_cmd_0x00000x00b6
100bcaec R __host_cmd_0x00000x00b7
100bcaf8 R __host_cmd_0x00000x00d2
100bcb04 R __host_cmd_0x00000x00d3
100bcb10 R __host_cmd_0x00000x00db
100bcb1c R __host_cmd_0x00000x0101
100bcb28 R __host_cmd_0x00000x0102
100bcb34 R __host_cmd_0x00000x0103
100bcb40 R __host_cmd_0x00000x0104
100bcb4c R __host_cmd_0x00000x0110
100bcb58 R __host_cmd_0x00000x0111
100bcb64 R __host_cmd_0x00000x0112
100bcb70 R __host_cmd_0x00000x0113
100bcb7c R __host_cmd_0x00000x0114
100bcb88 R __host_cmd_0x00000x0115
100bcb94 R __host_cmd_0x00000x0116
100bcba0 R __host_cmd_0x00000x0117
100bcbac R __host_cmd_0x00000x0118
100bcbb8 R __host_cmd_0x00000x011a
100bcbc4 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcbc4 R __hcmds_end
BRANCH=none
Change-Id: I5d13d2a7fe7fa9a0fbeed43177cc612f572a58bb
Reviewed-on: https://chromium-review.googlesource.com/419702
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit c459c8278e
as the fix is not straightforwad, some host command codes in
private repos are expressed using C preprecessor which
breaks the assumption of this patch that all host commands
are expressed as four digit hex numbers.
Change-Id: I922de9ae8dbab6eef048463c5c09b1f338152083
Reviewed-on: https://chromium-review.googlesource.com/414492
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chrome-os-partner:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
100bca94 R __hcmds
100bca94 R __host_cmd_0x0000
100bcaa0 R __host_cmd_0x0001
100bcaac R __host_cmd_0x0002
100bcab8 R __host_cmd_0x0003
100bcac4 R __host_cmd_0x0004
100bcad0 R __host_cmd_0x0005
100bcadc R __host_cmd_0x0006
100bcae8 R __host_cmd_0x0007
100bcaf4 R __host_cmd_0x0008
100bcb00 R __host_cmd_0x0009
100bcb0c R __host_cmd_0x000a
100bcb18 R __host_cmd_0x000b
100bcb24 R __host_cmd_0x000d
100bcb30 R __host_cmd_0x0010
100bcb3c R __host_cmd_0x0011
100bcb48 R __host_cmd_0x0012
100bcb54 R __host_cmd_0x0013
100bcb60 R __host_cmd_0x0015
100bcb6c R __host_cmd_0x0016
100bcb78 R __host_cmd_0x0017
100bcb84 R __host_cmd_0x0025
100bcb90 R __host_cmd_0x0026
100bcb9c R __host_cmd_0x0029
100bcba8 R __host_cmd_0x002a
100bcbb4 R __host_cmd_0x002b
100bcbc0 R __host_cmd_0x002c
100bcbcc R __host_cmd_0x0044
100bcbd8 R __host_cmd_0x0045
100bcbe4 R __host_cmd_0x0046
100bcbf0 R __host_cmd_0x0047
100bcbfc R __host_cmd_0x0061
100bcc08 R __host_cmd_0x0062
100bcc14 R __host_cmd_0x0064
100bcc20 R __host_cmd_0x0065
100bcc2c R __host_cmd_0x0067
100bcc38 R __host_cmd_0x0087
100bcc44 R __host_cmd_0x008c
100bcc50 R __host_cmd_0x008d
100bcc5c R __host_cmd_0x008f
100bcc68 R __host_cmd_0x0092
100bcc74 R __host_cmd_0x0093
100bcc80 R __host_cmd_0x0096
100bcc8c R __host_cmd_0x0097
100bcc98 R __host_cmd_0x0098
100bcca4 R __host_cmd_0x0099
100bccb0 R __host_cmd_0x009e
100bccbc R __host_cmd_0x00a0
100bccc8 R __host_cmd_0x00a1
100bccd4 R __host_cmd_0x00a8
100bcce0 R __host_cmd_0x00a9
100bccec R __host_cmd_0x00b6
100bccf8 R __host_cmd_0x00b7
100bcd04 R __host_cmd_0x00d2
100bcd10 R __host_cmd_0x00d3
100bcd1c R __host_cmd_0x00db
100bcd28 R __host_cmd_0x0101
100bcd34 R __host_cmd_0x0102
100bcd40 R __host_cmd_0x0103
100bcd4c R __host_cmd_0x0104
100bcd58 R __host_cmd_0x0110
100bcd64 R __host_cmd_0x0111
100bcd70 R __host_cmd_0x0112
100bcd7c R __host_cmd_0x0113
100bcd88 R __host_cmd_0x0114
100bcd94 R __host_cmd_0x0115
100bcda0 R __host_cmd_0x0116
100bcdac R __host_cmd_0x0117
100bcdb8 R __host_cmd_0x0118
100bcdc4 R __host_cmd_0x011a
100bcdd0 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcdd0 R __hcmds_end
BRANCH=none
Change-Id: Ideb9951b318763f71915e2c4e5052f4b4bfab173
Reviewed-on: https://chromium-review.googlesource.com/405528
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To reset the TPM task, we send it an event so that it will reset
only when it's not busy doing actual TPM stuff that might fiddle
with the stack or shared memory. But that means that we can't
always know when the task finally gets around to resetting
itself.
This CL adds a tpm_reset() function that blocks until the reset
actually occurs. Obviously it can't do that if it's being called
in interrupt context or from the TPM task itself, but otherwise
it does.
BUG=chrome-os-partner:52366
BRANCH=none
CQ-DEPEND=CL:361680
TEST=make buildall, test on Gru, manual tests
In addition to the normal rebooting, logging in/out, and so
forth. I added a temporary console command to call tpm_reset()
and scattered a bunch of ccprintfs around it. When called due to
SYS_RST_L, it didn't block. When invoked with the console
command, it did.
Change-Id: I51e8b1299dbdcd1a12273cf48a890e93ed32a8c8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/388125
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Rather than doing a full cr50 reset when the system reset SYS_RST_L is
asserted, just reset the state of the TPM task and library. Re-clear
.bss for those modules, then re-initialize.
BRANCH=none
BUG=chrome-os-partner:52366
CQ-DEPEND=CL:366792
TEST=make buildall; test on Gru
Trigger a SYS_RST_L by using the AP's reboot command, power
off/on, log in/out/in.
See that the Cr50 does not reboot and the firmware and userspace
are still happy about the TPM.
Change-Id: I32cd2bb72316f68c74db77a20a8d09112b402d4b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361680
We found the api utility in ROM doesn't enable burst mode of GDMA. It
influences the performance of FW download a lot. The CL modified GDMA
for moving the code of the other region from flash to ram. And move a
function that kicks off GMDA transactions to suspend ram in case this
utility is erased by itself. This issue will be fixed in our next
generation.
Modified sources:
1. system.c: Implement GDMA bypass.
2. system_chip.h: Import flash addresses for GDMA bypass code.
3. registers.h: Add GDMA register definitions.
4. cortex-m/ec.lds.S: Add lowpower_ram2 section in linker script.
BRANCH=none
BUG=chrome-os-partner:56794
TEST=make BOARD=npcx_evb; test sysjump and measure download time
Change-Id: I8490f8f2e5a8cdcb6fd10511878c4a4af8073bbf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381779
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a hook to act when the a device is going in tablet mode and back.
BUG=chromium:606718
BRANCH=kevin
TEST=Test with evtest that an event is sent to the AP.
Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380412
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Previously the maximum number of deferred routines was specified by the
the default maximum number of deferred routines you had to override
this, and if you wanted fewer, you still payed the price of having the
defer_until array statically allocated to be the maximum size.
This change removes that define and instead creates the RAM state of
the deferred routine (the time to wait until to call the deferred) when
the deferred is declared.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
manually test on discovery-stm32f072
Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc
Reviewed-on: https://chromium-review.googlesource.com/335597
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
If OUTDIR brings in a "@", the build breaks because that delimits the
path, leading to invalid file names.
This can happen (and happened) when building on a Jenkins CI instance
which uses jobname@number as path for parallel checkouts on a
single build node.
BRANCH=none
BUG=none
TEST=build with make out=foo@bar ... failed and works now.
Change-Id: Id0594f0d7312419110091443755ec11b5f8ee2d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/327110
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
There are hooks for chipset power sequencing but not one to indicate
that the system has reset at runtime. Add a hook for this and
implement for lm4 and mec1322. The hook is notified on any platform
reset, including those that happen on the way into S3/S5 state.
There is a new config variable added because the hook is notified in
the interrupt handler and needs a deferrable function that needs to
be added to every board.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315221
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.
This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.
To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.
Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.
A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.
BRANCH=none
BUG=chromium:43025
TEST=as follows:
- make buildall -j still succeeds
- verified that regular CR50 image starts successfully
- modified chip/g/loader/main.c to launch RW_B first, re-built and
re-run the image, observed on the console:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
cr50 bootloader, 20151118_11218@80881, no USB, full crypto
Valid image found at 0x00084000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
[0.001148 Inits done]
This FPGA image has no USB support
Console is enabled; type HELP for help.
> [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(note that the image base address is 0x840000, which is RW_B).
Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch introduces a facility which would allow to compile in
callbacks for arbitrary commands passed over various communication
protocols.
Typically this will be used for testing, when various test commands
are multiplexed over an existing protocol.
The callbacks are associated with 16 bit command codes. On input the
callback receives a buffer, containing the command's argument, the
size of the command argument and the maximum size of the buffer. On
output the callback stores processing result in the same buffer and
updates the size to the actual amount of returned data.
Callback descriptors are stored in a dedicated read only section which
is scanned by extension_route_command() to find a callback associated
with a certain command code.
A console channel is also being introduced to allow controlling
console output generated by extension commands handlers.
BRANCH=none
BUG=chrome-os-partner:47524
TEST=none yet
Change-Id: I8ae16a78ca7d72176a5e7f74dd7a232078e7c06c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/312586
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the proper RO in place, RW must be signed in the same manner, as
RO. This patch makes sure that there is room in the RW header for the
signature.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with the rest of the patches applies the RO successfully boots up
the RW.
Change-Id: I1538195e0181c23c874ddd300887cf5da8c5a867
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311421
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The point at which we reloaded the loader was too early. When items are
placed into .bss.slow via CONFIG_REPLACE_LOADER_WITH_BSS_SLOW, other
tasks could still access their variables that may have been in that
region after we had replaced those contents with the loader. This
commit moves the reloading of the loader to as late as possible once all
tasks have done their HOOK_SYSJUMP work.
Also, fixed a bug with the .bss.slow section. If a board is not using
the config option but items are placed in that section, that part of RAM
would not be cleared out.
BUG=chrome-os-partner:46056
BRANCH=None
TEST=Enable config option on GLaDOS and add a few variables to the
.bss.slow section. 'sysjump' between RO and RW and verify that no data
bus error is encountered.
TEST=make -j buildall tests
Change-Id: I3084700b9d5c144e86e2e408b72d2e3075a67413
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/306173
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Certain ECs which cannot load both the RO and RW images into memory
simultaneously have a little firmware (LFW) loader that is loaded into
the beginning of the program memory. This loader is responsible for
loading the RO/RW images, however once we begin executing code from
main(), the loader has already completed it's purpose. We can reuse
this space by allocating portions of the .bss section here. This
currently saves us 3k for mec1322. This section is .bss.slow.
To use this feature simply define the following config option in
board.h.
#define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW
In some cases, such as the mec1322, this region of RAM is optimized for
code and not data. Therefore, ideally infrequently used data should go
into this region.
BUG=chrome-os-partner:46056
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Flash GLaDOS; sysjump rw; Verify that we are in rw; sysjump ro;
Verify we are back in ro.
TEST=Build GLaDOS, check output memory map for LDR_REGION and .bss.slow
section.
TEST=make -j buildall tests
Change-Id: I5b95cacc211278cf780a857b5a2ecfc1a0a28c45
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/305254
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
For signed EC RW images (CONFIG_RWSIG), there's no point in
embedding the public key or signature into the image itself since
it will just be replaced by the signer (either as the next step
in the build process, or after the fact for MP releases). This
takes that out and just points to where the pubkey and signature
will be placed.
BUG=none
BRANCH=none
TEST=make buildall
I also checked the signatures with
futility show -t build/*/ec.bin
They still look good, and the one signed image I booted (Cr50)
works as before.
Change-Id: Ib39b7c508914851f81a1bebb2450e08ef0def76c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302630
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The board-specific board.h defines things like this:
#define CONFIG_RO_SIZE 1000
#define CONFIG_RW_SIZE 1000
#define CONFIG_SHAREDLIB_SIZE 200
And in the linker scripts we define some preprocessor macros like
so:
#define FW_SIZE_(section) CONFIG_##section##_SIZE
#define FW_SIZE(section) FW_SIZE_(section)
So that we can say things like this:
FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
Note that we have to use FW_SIZE, not FW_SIZE_
The difference is only noticeable when SECTION is #defined. If
${CFLAGS} has
-DSECTION=RW
Then the expansion is this:
FW_SIZE_(SECTION) => CONFIG_SECTION_SIZE
FW_SIZE_(RW) => 1000
There's no difference in the output for this particular CL, but
we should use the correct macro anyway to avoid confusion.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I61edc76a1aaeb1c675b384371700f37dda39ed47
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/302150
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When we add head room to the RO image, it's generally to provide
a chip-specific boot header of some sort. That header is only
needed for the RO image, not the RW image. The macro name implies
this, but this CL makes it so.
BRANCH=none
BUG=chrome-os-partner:43025, chrome-os-partner:44625
TEST=the cr50 image validates *and jumps to* the RW image at boot.
Change-Id: I0e5b2c32e232418970e01c7409ddcbbabd4786d5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296451
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Some platforms might expect the header of the image to be a certain
platform specific blob. This patch adds an ability to insert an
arbitrary size header in the binary blob, if so desired, the intention
is to have the platform specific tools to postprocess the image and
replace the header with sensible data.
Ideally we should be able to produce an image which is mapped to start
at an offset to the FLASH_BASE, but the macros in ec.S.lds files are
way too smart for this.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=with this and other changes the latest cr50 image gets signed and
booted properly.
Change-Id: Icabf00c6b90657b0ae3370ddad3567ccedf3ff49
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/295200
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit introduces the build infrastructure changes needed for
creating a shared RO library. (libsharedobjs). The end goal is for the
library to contain various objects that can be shared with both the RO
and RW EC images.
Now, there are 3 make goals: ro, rw, and libsharedobjs.
In order for changes that are only specific to a single image (ie: RW
only) to be applied correctly, the object files are now built separately
for the RO, RW, shared objects library targets.
NOTE: Certain EC targets are incompatible with this model due to the
fact that only one image is present within flash at a time.
BRANCH=none
BUG=None
TEST=make -j buildall tests
TEST=make -j BOARD=cr50 xrefs
TEST=make BOARD=samus dis
TEST=Built samus EC image and compared that the final EC image was
identical to the upstream version (except for the git SHAs & version
strings).
CQ-DEPEND=CL:285934
Change-Id: I8e67f089710be9c6d7017718109262394bdad2f5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/274079
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Add npcx_evb_arm board-level driver for arm-based platform.
Add header.c: for booting from NPCX5M5G A3 Booter.
Remove lfw folder due to those functionalitie have been replaced with Booter
Modified drivers for
Patch Set 1:
1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities
2. hwtimer.c: Add ITIM32 for hwtimer
3. lpc.c: Add checking for LRESET
4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter.
5. uart.c: Add support for module 2
Patch Set 2:
6. lpc.c: Modified lpc_get_pltrst_asserted() func
Patch Set 3:
7. minimize the changes for CONFIG_CODERAM_ARCH in common layer
8. comments of Patch Set1/2
Patch Set 4:
9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat.
10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH.
Patch Set 5:
11. Modified system.c in common folder for supporting *_STORAGE_OFF.
12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash.
Patch Set 6:
13. rebase to newest version
14. system.c: Modified for the newest include/system.h
Patch Set 7:
15. Merge from version 0625
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/272034
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Our USB buffers are just arrays of uint8_t in program RAM, so
let's treat them that way. The DMA descriptors are in normal RAM,
too.
BUG=chrome-os-partner:40693
BRANCH=none
TEST=make buildall
Change-Id: Ibafe1a557a328bbf8cf37ce113675fcd35bad376
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273918
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.
CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image
CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image
CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Currently, ECs with internal flash store the write protect state for
RO in a separate write/erase block of flash. This is wasteful on
chips where there are not many blocks of flash.
Add a new CONFIG_FLASH_PSTATE_IN_BANK option which is defined by
default. This is the old behavior, for compatibility. (And we're
calling it 'bank' because that's what the existing code does, even if
the terminology is somewhat etymologically... bankrupt.)
If that config is #undef'd, then store the write protect flag directly
inside the RO image. This uses only 4 bytes of the RO image, instead
of an entire erase block. The magic numbers for the pstate values are
chosen such that when protecting RO, bits are only transitioned away
from their erased state. Unprotecting RO once it's protected requires
reflashing RO; it's no longer possible to 'flashwp disable'. But
that's ok, because realistically, the only reason to unprotect RO is
if you're about to flash the RO firmware anyway.
BUG=chromium:476659
BRANCH=none
TEST=Without undefining CONFIG_FLASH_PSTATE_IN_BANK, make sure everything
still works on samus and samus_pd. This ensures we didn't break the
existing functionality:
flashinfo -> no flags
flashwp enable
flashinfo -> ro_at_boot
reboot
flashinfo -> ro_at_boot
flashwp disable
flashinfo -> no flags
Then recompile with #undef CONFIG_FLASH_PSTATE_IN_BANK and test:
flashinfo -> no flags
flashwp enable
flashinfo -> ro_at_boot
reboot
flashinfo -> ro_at_boot
flashwp disable -> fails with access denied
flashinfo -> ro_at_boot
Then reflash to verify that clears the ro_at_boot flag:
flashinfo -> no flags
Change-Id: Ie794b8cfed2a10c50b0e36dcf185884070b04666
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/266095
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
This was causing the amount of data sent to be larger than the
total size of the descriptors.
Before this CL, connecting the Cr50 through USB gave this kernel
message:
usb 2-1.4.7: config 1 descriptor has 1 excess byte, ignoring
When the host requests the descriptor, the code in chip/*/usb.c
that handles it looks like this:
case USB_DT_CONFIGURATION: /* Setup : Get configuration desc */
desc = __usb_desc;
len = USB_DESC_SIZE;
break;
But include/usb.h has this:
#define USB_DESC_SIZE (__usb_desc_end - __usb_desc)
And both __usb_desc and __usb_desc_end come from the linker
script.
BUG=none
BRANCH=none
TEST=manual
Before this change, I built the Cr50 firmware from m/master,
tried it, and got the dmesg complaint on the host.
After this change, the dmesg complaint doesn't show up anymore.
Change-Id: I83ae2333a9e76af7acb18bd2f0e4cef5c095862a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/265765
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add hook for battery state of charge change. Hook will be used
to cleanup the samus charging workarounds to follow.
BUG=none
BRANCH=samus
TEST=make -j buildall
Change-Id: I99cbb8264783802139cac689804b056623063695
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/245252
Reviewed-by: Shawn N <shawnn@chromium.org>
Add npcx_evb in board folder for testing
Add shared-spi arch support in common layer.
Modified drivers for
1. Fan.c: console command “pwmduty”.
2. Pwm.c: for the issue when set duty to 0.
3. System.c: for hw reset only during system reset.
4. Flash.c: Fixed access denied bug of the flash driver for host command.
5. Comments from Patch Set 1
6. Comments from Patch Set 3 (except sha256.c)
7. Add openocd and flash_ec support for npcx_evb
8. Add little FW and spi-flash upload FW in chip folder
9. Add optional make rules for PROJECT_EXTRA
10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes
in common layer sources for shared-spi arch. (except sysjump)
11.Find the root cause of JTAG issue and use workaround method
with SUPPORT_JTAG in clock.c
12 Execute hibernate in low power RAM for better power consumption
13 Add workaround method for version console command
14 Modified coding style issues by checkpatch.pl tool
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I5e383420642de1643e2bead837a55c8c58481786
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/233742
Allow to use larger RSA keys by setting CONFIG_RSA_KEY_SIZE to 4096 or
8192 rather than using the default 2048-bit size.
It's mainly for benchmarking purpose right now as we don't have the RAM
to store the 3x key size buffer and the flash space for the public key
structure.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=build Zinger with CONFIG_RSA_KEY_SIZE equals to 4096 and run it.
Change-Id: I9839121bf158d0a30dde1e48d875f345191bfec2
Reviewed-on: https://chromium-review.googlesource.com/228925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Previously the USB RAM size was off by a factor of two
for chips that required 32-bit alignment of accesses,
even though the underlying memory was 16-bits in size.
This change adds an additional configuration for the
access size (it still assumes that the underlying memory
is 16-bits in size) and uses that to adjust the USB_RAM
memory section in the linker scripts.
This change also removes the default values for the USB
RAM from stm32/config_chip.h because they mask issues
when new chips are added. It is better for a new chip
to fail to compile until these values are provided.
Finally, this change introduces a common USB API header
so that common code doesn't need to include the STM32
specific header.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: Id118627f53e9e8ff1bd09fb51f1f9634ff495d19
Reviewed-on: https://chromium-review.googlesource.com/228833
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
This implements a new API for EC modules to define MKBP event sources
and send MKBP event to the AP. Also, a new host command
EC_CMD_GET_NEXT_EVENT is added for the AP to query the pending MKBP
events. Each event type may have custom event data sent along with the
event.
BRANCH=None
BUG=chrome-os-partner:33194
TEST=Enable MKBP event on Ryu. Set a host event from EC console, run
'ectool nextevent', and see MKBP event 0x01 (HOST_EVENT) and the set
host event.
Signed-off-by: Vic Yang <victoryang@chromium.org>
Change-Id: I28a1b7e826bcc102bbe39016c9bb3e37d125664c
Reviewed-on: https://chromium-review.googlesource.com/224905
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The Zinger RW is now signed with 2048-bit RSA key (using SHA-256 as
digest).
This CL implements the verification mechanism.
note: the RSA key used for signing must be provided as a .pem file.
The path to .pem file must be provided in the PEM environment variable.
By default, it's using the dev key stored in zinger_dev_key.pem.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:28336
TEST=on Zinger, run with properly signed RW firmware and corrupted
firmware and check the serial traces.
Change-Id: Ia58482458904a3ed72d6b0e95996cae86a0ead83
Reviewed-on: https://chromium-review.googlesource.com/220178
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Enough USB support to be able to enumerate the device and use bulk or
interrupt endpoints.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28295
TEST=with the following USB console CL, connect a Fruitpie through USB
and use its console over USB.
Change-Id: I37b7f3b6a754cb82ab5f940ea20122d2e16b3b5b
Reviewed-on: https://chromium-review.googlesource.com/193983
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Put each functions in a separate section by using -ffunction-sections,
then discard the non-referenced ones in the linker with -gc-sections.
Force keeping a few special symbols by using the KEEP() linker
directive.
This modification is not saving a lot of spaces per se, but will enable
larger code pruning with future optional features.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall, manually check discarded symbols in the .map file
and run on Spring and Link.
The size delta is the following:
Link: total 85.7k -> 84.9k (.text 60.3k -> 59.5k)
Spring: total 59.2k -> 57.2k (.text 44.4k -> 42.5k)
Change-Id: Ib6eb0d3f2cc4fc172c9fc26acac2e486921690a3
Reviewed-on: https://chromium-review.googlesource.com/189224
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
