We can clear the reset cause in system pre-init now because of a
previous change which preserves it across a sysjump.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=if it boots, it works
Change-Id: I1d8b99df5a0be0de9545d22ad1a6b7fb3140f813
This will be used for sleep/wake/sysjump/etc. For now it's just wired
up to clock frequency changing.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual: use nopll command, should still work
Change-Id: Iedcea5830bc18eacfd955c29b8f793aba8905dd8
Adding trickle charging mode to precharge batteries with
voltage lower than minimal design value. This CL adds
control to charger voltage to track battery input current
change.
To prevent battery from deeply discharging, this CL preserves
3% of the design capacity.
Minor bug fixes include error state check and charger control
logic.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8660,8661
TEST=manual
Plug AC power, the power adapter led should be
'yellow'. On the EC serial console, type 'battery'
and 'charger' commands.
Battery input current should staid close to its
desired current.
A deeply discharged battery (5.5V) should be revived to
a healthy state after 30 minutes ~ 4 hours.
Change-Id: Ibaa2396c6b751639d98db32f5919b1e8ec700e40
The reboot_ec command could warm boot the EC while the host is still
running. However, this resets the internal state so that the keyboard
module is disabled on the EC side.
Check the reset cause during the keyboard init code. If it is wrm boot,
enable the keyboard (assume the host is on).
BUG=chrome-os-partner:9102
TEST=on link 1.0
% ectool version
Firmware copy: RO
% ectool reboot_ec RO
the keyboard keeps working.
Change-Id: I0009c561e2cd88789e50f9129b494538e50ee00e
This patch adds explicit handling of open-drain outputs
and adds Hi-Z for high-impedence state (floating) outputs.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=compile tested
Change-Id: I1a0c2e8366f6a82cd9cd7e83e57122944f2bdc2d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7832
TEST=manual
1. Power on system
2. From ec console: kblight 100
3. Use a magnet next to the left shift key to trigger the lid switch. Screen and keyboard should go dark.
4. Remove the magnet and they should light up again.
Change-Id: I298ea94930976153d8dcd102316b010ee28cd747
Add a SPI driver which can receive and process commands, and provide
responses using the message interface.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: I286da803b85640525607de6c4d41f0629f7006dc
Signed-off-by: Simon Glass <sjg@chromium.org>
I need to clean up the console commands and provide the same functionality
via ectool, but this is a good starting point.
BUG=chrome-os-partner:7839
TEST=manual
Power up the CPU. The lights should blink.
Change-Id: Ic05a171d2b647551f1cfc7d6b2fd101088cac137
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8971
TEST=manual
waitms 1500
(see watchdog trace)
waitms 1500
(should see watchdog trace again)
waitms 3000
(should see trace, then system should reboot)
Change-Id: Ieb5009d7a7bc9e1ed795e58efb0cb44a1eeb2706
Provide the required plumbing for the stm32 keyboard scan code so that
the message layer will pick up keyboard scans.
The design is as follows:
- When a change in keyboard state is detected, the keyboard matrix
scanning code will call the board-specific board_keyboard_scan_ready()
function to interrupt the AP.
- The AP will initiate a CMDC_KEY_STATE transaction over SPI or I2C
- The SPI or I2C driver will call message_process_cmd() to process the
command
- This in turn will call keyboard_get_scan() to get the latest scan data
For SPI:
- The AP will initiate an 20-byte (or longer) SPI transaction
- The EC will see the command, and provide the keyboard state in response,
with the response being part of the same transaction
For I2C:
- The AP will initiate a 1-byte write to set the EC mode.
- The AP will then initiate an 18-byte read, and the EC will send the
message including keyboard state
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: I905ef9d567e43d85fb851052f67586eff58e1167
Signed-off-by: Simon Glass <sjg@chromium.org>
Whatever means is used to talk to the AP there is no justifcation for
putting message processing directly in drivers. Create a suitable
header file to define the interface, and provide a processing function
which can provide responses to incoming messages.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: If09ea3e30d42d8c5f226dc4421d4895adc54f937
Signed-off-by: Simon Glass <sjg@chromium.org>
Add nopll command to turn off the PLL, reducing the system clock to 16Mhz.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8798
TEST=manual
boot system
press power button to boot x86
temps // should print all temperatures
timerinfo
timerinfo
timerinfo // convince yourself this is counting up at about 1MHz
nopll // this drops the system clock to 16MHz
temps // should still print all temperatures
timerinfo
timerinfo
timerinfo // should still be counting up at about 1MHz
Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
- The max IO buffer size in ACPI is 255/0xFF bytes.
- The ACPI ASL code in coreboot is pre-processed to handle
constant #defines, but the IASL compiler cannot handle any
actual C code so add an __ACPI__ guard.
BUG=chrome-os-partner:7734
TEST=include this header in coreboot and compile successfully
Change-Id: Ife61935cec1a39f072625c2788f70487c3559060
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Add a host command returning chip information. The interface is in common/
while the implementations are in chip-specific code (note: added simple
value for stm).
BUG=chrome-os-partner:8567
TEST=on board
% ectool chipinfo
Chip info:
vendor: xx
name: yyyy
revision: zzzzz
Change-Id: I5030a03a6fcfbfc080d5acd8efb763fde7eefde5
This data is used to populate the _BIF/_BIX packages in ACPI
but it currently needs an EC command to retrieve that isn't
easy to query in ACPI since it isn't using standard EC RAM.
1) Export these additional fields in init() state:
- Design Capacity of Full
- Design Voltage
- Last Full Charge Capacity
- Cycle Count
- Manufacturer String
- Model String
- Serial Number String
2) Fix an issue where battery current was not reported when
the battery was charging.
3) Remove the command interface so there is no duplication.
BUG=chrome-os-partner:7734
TEST=using (not yet published) coreboot to read battery status
via ACPI and verify that battery removal/insertion events
are properly handled.
Change-Id: If337aad3255e5b1a0f85168838f1dd86a32bbeb3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7461
TEST=manual
make BOARD={bds,link,daisy}
make tests
flash link system and make sure it boots
Change-Id: I1241a1895c083e387e38ddab01ac346ca4474eb9
Factor out fan speed control for easier adjusting fan speed stepping.
Also increase number of fan speed steps from 2 to 5.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Manual test.
Change-Id: I0ff601c0a4f2ed2a4867bdc6e550eb2827404754
BUG=chrome-os-partner:8728
TEST=manual
I don't have a system that has both an EC and a lightsaber, so I can't be
certain this works, but I *think* it will.
I do have a Link proto 0.5. With that, you can say
ectool lightbar test
and the EC console says it's poking at the lightbar, but of course there's
nothing there. If there was, it *should* flash in pretty colors. I have a
lightsaber attached to a BDS, and from the EC console running "lightsaber
test" does make it blink.
Change-Id: Ib6021ad8e53959de52b12efda376254071e5fb4b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
This reverts commit dfe22b2b1e.
We seem to have solved I2C block issue. Reverting the workaround LPC
command and ectool command.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8239
TEST=Compilation succeed. Manually tested temperature polling still
works.
Change-Id: I0acb567a138282479c7cc07cbfa723c439d04cd7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8724
TEST=if timestamps show up in the debug output, it works
Change-Id: I5264a3a40a07a824cc15b39a7bd81f2db02a3c13
BUG=chrome-os-partner:8718
TEST=manual
1) Use 'reboot' command from console to boot image. Should end up in
image A, with last reset reason soft cold. 'sysinfo' should show we
jumped to this image.
2) sysjump RO. Should end up in RO; otherwise same as 1)
3) reboot using Power+Esc+Reload. Should end up in image RO, with last
reset reason reset pin. 'sysinfo' should show we did not jump to this
image.
4) sysjump A. Should end up in A with reset reason reset pin.
'sysinfo' should show we jumped here.
Change-Id: I2dd5595eab4ba2c91bfe8b2b2e9677d7732aca63
Signed-off-by: Randall Spangler <rspangler@chromium.org>
This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
Comapre the range to be write (erase) with the range of active image.
If overlap, return error to indicate the access denied.
Note that we actually protect only runtime code and ro data.
FMAP is intentional unprotected so that flashrom can update to new map
before jumping. Since the vector table and init code are in the same
erase page, they are unprotected as well.
BUG=chrome-os-partner:7478
TEST=
Change-Id: Icb5cc89836432a11cef80e18eb66bb39a6c9b1d9
This is necessary at init-time for verified boot to jump from RO to
one of the RW images.
It's also used by factory EC update to update one image and then jump
to the updated image to finish the update. In this case, the x86 does
NOT reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8449
TEST=manual
1) power on x86 and log in
2) sysjump a --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted
Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
This CL adds battery SMI events. And refactors the charging state
machine by adding share state context for all handlers.
Power events are moved to common handler. Minor clean up on console
output messages.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:7526,7937,8450
TEST=manual:
Watch console message when connecting/disconnecting AC adapter and
battery. Check the state transition.
Change-Id: I42eec4f87a9d49bd193cb9dde9080e3dfccbb77c
Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Group temperature sensors into different types so we only have to set
temperature threshold for each type instead of each sensor.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8466
TEST=Fan control still works.
Change-Id: I7acc714c32f282cec490b9e02d402ab91a53becf
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Keyboard reset now triggers a cold reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then do 'x86reset cold' for a cold reset or
'x86reset warm' for a warm reset. Check x86 debug console to see that
coreboot detects the warm (soft) reset.
Change-Id: I00930d9f5df98365277cd5c7f2eb8f135c4e4398
Until we solve the I2C hanging issue, we need a reliable way to read
temperature. Add back LPC temperature read command that actually trigger
a I2C read.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8452,chrome-os-partner:8495
TEST=none
Change-Id: Icddd1fe3c1f09889bca633af19041a8aca582de9
Make temp sensor report 0xfd when sensor is unpowered.
Also refactor power specification of temp sensors from thermal.c to
temp_sensor.c.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:8279
TEST=none
Change-Id: Ib13813bdbac2f048fbc3b98fae5bbf104ebf37d7
(new method, and x86reset command to call it)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8460
TEST=manual: powerbtn, wait for system to boot, x86reset
Change-Id: Iad3f5c268b334e8d0ec1adfa2878f9e9d5927b9f
Note that this is a big security hole and should be removed after we
complete the EC autoupdate mechanism and vboot code.
To full update EC firmware on proto 1.0, we need a manual way to switch
EC running on RO/RW. This CL implements the LPC command.
BUG=chrome-os-partner:8415
TEST=on proto 0.5.
ectool reboot_ec RW_A # EC boots to RW A
ectool reboot_ec RO # EC boots to RO
Change-Id: Ibf050328bc4e3d2c6d72bfc478d6334f11f0eb46
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
This CL adds LPC commands to provide the following information:
- Design Capacity (dword)
- Last Full Charge Capacity (dword)
- Design Voltage (dword)
- Design Capacity of Warning (dword)
- Design Capacity of Low (dword)
- Battery Type (ascii)
- Model Number (ascii)
- Serial Number (ascii)
- OEM (usually Vendor) (ascii)
- Battery charge cycle count (dword)
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8181
TEST=none
CQ-DEPEND:Iad4d63c996272568b5a661a6716790ef151b29c5
Change-Id: Iabaf7d9862e15c5b21cf5170cf43450e472b7836
These bits are as per definition in "Chrome EC LPC Communication"
document.
BUG=chrome-os-partner:8351
TEST=manual
. tested in concert with coreboot modifications introducing the EC
command implementation
Change-Id: I46d5795e06854e34584132c7fdb37e29150ce179
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8321
TEST=manual:
type 'battery' in EC serial console, check following fields:
Manufacturer
Device name
Device chemistry
CQ-DEPEND:I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Change-Id: Iad4d63c996272568b5a661a6716790ef151b29c5
Implement a generalized I2C transmit-receive function that
write-then-read blocks of raw data. Original 8-bit and 16-bit
read/write functions are refactored.
SMBus read-block protocol for ASCII string is also implemented
based on this API.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8026,8316
TEST=manual:
Type 'lightsaber' to check 8-bit read/write.
Type 'charger' to check 16-bit read.
Type 'charger input 4032' to check 16-bit write.
Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Note that this only handles lid and power button; see
crosbug.com/p/8325 for write protect.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8185
TEST=manual
1. Check state with lid open
localhost ~ # ectool switches
Current switches: 0x01
Lid switch: OPEN
Power button: UP
Write protect: ENABLED
2. Press power button
localhost ~ # ectool switches
Current switches: 0x03
Lid switch: OPEN
Power button: DOWN
Write protect: ENABLED
3. Release power button and close lid
localhost ~ # ectool switches
Current switches: 0x00
Lid switch: CLOSED
Power button: UP
Write protect: ENABLED
Change-Id: I25f2fa3dfeac004dde9b10a4243ee235875f1b6e
Useful when debugging to determine if a user has an official build or
not, particularly early in the devel process where we're handing
builds to everyone. Particularly useful for proto1, since not all
those systems will be case-open servo-attached.
Also move get-version LPC command into system.c, where it's closer to
the system functions it calls (matches what we do for other host
commands).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: Idb0f6edf31ca00e32f083be0b0d3f23ab79c5fba
...since x86_power_in_S0() is a terrible function to have implemented
for gaia chipsets, and I need to add more detectable states for lid
switch handling anyway.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I0c90c6875b27d1bf23f093e88e34eabf2a8c86e4
