When EC receives many flash write requests from host and
PDCMD, CHARGE and USB_CHG_P0 tasks are all ready to run, the
HOOK task may not get scheduled in time to pet the watchdog
resulting in an EC reset.
BUG=chrome-os-partner:51438
BRANCH=None
TEST=Manual on lars, determine two EC versions that have enough
differences so that replacing one image with the other will
require all or most of the flash pages to be updated. Alternate
between flashing the two images with flashrom using a script.
Atleast 1000 iterations should pass.
Change-Id: I8b5c8b680a2935b945f3740e371dee2d218ec4c5
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/334457
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit a537d1ac44c40e7f6e1131e8cc852b030ccdba52)
Reviewed-on: https://chromium-review.googlesource.com/334903
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
We clear global NAKs by writing bits in the USB_DCTL register.
However, prior to this CL we were overwriting the entire
register, not just touching individual bits.
Since we've never actually set any global NAKs, this mistake
didn't have any noticeable effects. But we should still do the
right thing in case we need it later.
BUG=chrome-os-partner:50721
BRANCH=none
TEST=make buildall; test on Cr50
No visible change; everything continues to work.
Change-Id: Ia25d95dc6211e5460132622ac005723f43b00e24
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335190
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We were referring to unhandled USB control messages as errors,
but they aren't necessarily. Sometimes they're optional things
that aren't fatal. We should still address them, but we don't
have to freak out.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50
Change-Id: I892acec2d89b8ec95353cdc09f3e49aa78b1704d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335200
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There were some unnecessary shifts and conditionals. This just
makes the code a little more readable.
BUG=none
BRANCH=none
TEST=make buildall; test on Cr50 hw
Change-Id: I084f191675d1b51101e9dc55c2e5a12b0b345d33
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334870
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This config option allowed us to disable the TPM protocol on the
SPI slave bus and replace it with our EC-style host command
protocol. We only used this for early testing and don't need it
anymore, so we can get rid of it completely for this SoC.
BUG=none
BRANCH=none
TEST=make buildall; test on cr50
Change-Id: I2126537e8bcc78e583cf426a3a83962c9ff1a121
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334762
Reviewed-by: Scott Collyer <scollyer@chromium.org>
BRANCH=none
BUG=none
TEST=Test OK on ITE8390CX.
You can run "make -j BOARD=it8380dev" to build ec.bin
and flash the ec.bin via
"sudo ./build/it8380dev/util/iteflash -w ./build/it8380dev/ec.bin"
Change-Id: I2077012114bdbd5a8cc8f7dc29e43cdcb77d65b6
Signed-off-by: Donald Huang <donald.huang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/334176
Reviewed-by: Randall Spangler <rspangler@chromium.org>
On oak battery, when the battery is dead it reports 0 for desired
voltage, current, and state of charge. In this case we should allow
charging.
Added a CONFIG option for this that should be removed as soon as
the battery side is fixed.
With this CL, when a dead oak battery is used and a charger is
connected, we attempt to charge it.
BUG=chrome-os-partner:51454
BRANCH=none
TEST=test on an oak with a dead battery. w/o this CL, the battery
never charges because the charging not allowed flag is set. With this
CL, the battery charges.
Change-Id: If9f1250cd41aec265838e1d109f53c1bcd58c111
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/334471
Reviewed-by: Rong Chang <rongchang@chromium.org>
1. Always use wake-up control interrupt for keyboard KSI. This can also
wake-up EC from deep doze / sleep mode.
2. In keyboard ISR, we just clear interrupt status to prevent keyboard
interrupt can't be re-enabled.
(for example, a KSI interrupt wakes up keyboard scan task,
but keyboard_raw_read_rows() got 0.)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=keyboard function is normally.
Change-Id: If8c292189c6133b179a63dedcb7a18abbc091312
Reviewed-on: https://chromium-review.googlesource.com/333865
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The channel enum and string name array were out of sync (when
CONFIG_EXTENSION_COMMAND is defined). This was caused by the two lists
being specified separately. I argue that this is a good reason to merge
the lists into a separate X-Macro include file.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I81d143f550a0fe6ef0c64e3c8357ed18aee4bfdc
Reviewed-on: https://chromium-review.googlesource.com/334381
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
isl9237 uses HW ramping but has no way to monitor the ramp current. Zero
is not a good estimate of the ramp current and scares users into
thinking their device isn't charging, so use the nominal current limit
instead.
BUG=chrome-os-partner:51286
BRANCH=Glados
TEST=Verify "ectool usbpdpower" on chell reports "14xxxmV / 2668mA"
rather than "... / 0mA" with stock charger attached.
Change-Id: I0a29c8092b4994fda68dc3db8e02be2e0f234fd9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334237
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit cef36e872f72db9e060dd0cc7e5bced3062fbfd1)
Reviewed-on: https://chromium-review.googlesource.com/334395
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Re-write smbus driver to fix arbitrary length read and improve code
organization.
BUG=chromium:576911
BRANCH=None
TEST=Manual on sentry. Verify that smbus communication with battery is
functional.
Change-Id: I63c4bc3df40755cd41b3d9956af0ab9d2145a253
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333787
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Building a single buffer for crc calculation is often inefficient, so
add a new function that calculates crc8 from an existing crc8.
BUG=chromium:576911
BRANCH=None
TEST=Manual on sentry with subsequent commit. Verify that smbus
communication with battery is functional.
Change-Id: I05ffedb81ffcf0c126acda5f6212b3147b1580a1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333786
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
`tempsinfo all` will probe all 24 sensor IDs, which will produce stderr
output due to host command failure if a given sensor does not exist.
Therefore, check memmap data for presence before probing a given ID.
BUG=chrome-os-partner:51026
BRANCH=None
TEST=Manual on Sentry. Verify "ectool tempsinfo all" dumps info on 4
temperature sensors and prints nothing to stderr.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I14d65c1ad03eafafc21db41781c434b3ed74cb7e
Reviewed-on: https://chromium-review.googlesource.com/333779
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
During the resume sequence of S0ix EC can receive host commands early
in the resume path when LPC is still disabled in EC. Host messages
will be lost if the LPC interface with the kernel is down.
Clock control was programed to 2 which means ring oscillator is
shut down after completion of everty LPC transaction.To restart
the oscillator EC should enable a wake interrupt on LPC LFRAME number
and this mode can cause an increase in the time to
respond to the LPC transactions.
Keeping LPC always on shows minimal power impact as per datasheet
Pg.390. The impact is < 0.45mW.
BUG=chrome-os-partner:50627
TEST=Enter into S0ix and exit reliably.
BRANCH=firmware-glados-7820.B
Change-Id: I670b9b45c3a85c9bca249312a73a25dca52b313a
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332333
Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c03fd6e0eaa6ecd3205214f901facb9896a798b4)
Reviewed-on: https://chromium-review.googlesource.com/332791
* Update flash_ec to allow flashing servo_micro
* Add servo_micro build
BUG=chromium:571477
BRANCH=None
TEST=updated servod is able to control gpio, gpio extender,
SPI flash, ec uart, ap uart on test yoshi
Signed-off-by: Nick Sanders <nsanders@google.com>
Change-Id: I4d69c83ae581cb41da928a27c39b7152475d7ca8
Reviewed-on: https://chromium-review.googlesource.com/327214
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The debounce timer might be too slow to actually update the state of
debounced_power_pressed by the time we do power_button_is_pressed in
the S3->S5 state transition.
Call power_button_wait_for_release() instead of wait_for_power_button_release()
to make sure there are no deferred actions.
BRANCH=none
BUG=chrome-os-partner:50362, chrome-os-partner:51109
TEST=During dev mode screen, press power button, note the device stays off
TEST=sudo test_that -b oak <DUT_IP> firmware_FwScreenPressPower
Change-Id: Ic60c1847ba461ef874dea5bf7d03675622f24beb
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332310
Reviewed-by: Rong Chang <rongchang@chromium.org>
CONFIG_PMIC_FW_LONG_PRESS_TIMER was ported long time ago from
Tegra, but the codes are actually not used and erroneous.
It might wrongly trigger set_pmic_pwron(0), and turn off
PMIC power accidentally. This causes POWER_GOOD lost and
power state will go back to S5 during boot up.
Clean up the codes by referencing check_for_power_off_event()
of Rockchip.
BRANCH=none
BUG=none
TEST=bootup and press power button quickly right after we are in S0.
Bootup should still complete normally.
Change-Id: Ie034efa3575dbebae4debb1afc206fddd9116350
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332724
Reviewed-by: Rong Chang <rongchang@chromium.org>
After power good is lost, PMIC requires some time to turn off
all its internal power before we can turn off VBAT by
set_system_power(0). This ensures the power measurement is within
PMIC spec when system is shut down.
BRANCH=none
BUG=none
TEST=measure the power rails of PMIC after system is shut down
Change-Id: I55d4d99ed0ef69b103a4e52e9f9eec1c9e6265b5
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332409
Reviewed-by: Rong Chang <rongchang@chromium.org>
Increase LED blink cycle time to reduce power consumption on Oak rev5
with GlaDOS ID.
BUG=chrome-os-partner:50317
TEST=`make EXTRA_CFLAGS=-DBOARD_REV=5 BOARD=oak -j`
Change-Id: Ic00512434965471a82b94ef431e0ec88c9e4c0c3
Reviewed-on: https://chromium-review.googlesource.com/332346
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Since npcx5m6g has larger than 128 KB code ram for FW, the original
alignment between RO & RW regions isn't suitable for new chip.
Therefore, we add 256KB alignment of them for npcx5m6g.
In order to program the flash used by npcx5m6g, we add new board array,
BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout
ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g
and flash_npcx5m6g to program flash with different layout.
Modified sources:
1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for
npcx5m6g.
2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to
distinguish which flash layout ec used.
3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with
different layout.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/331903
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a usb endpoint and class for i2c control via USB.
Used for servo micro and servo_v4 to export USB control
through servod.
BUG=chromium:571477
BRANCH=None
TEST=updated servod is able to control gpio extender on servo_micro
Signed-off-by: Nick Sanders <nsanders@google.com>
Change-Id: Id44096f8c9e2da917c0574d28dfcbcc0adf31950
Reviewed-on: https://chromium-review.googlesource.com/329322
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Currently when in suspend the LED blinks white no matter what the
state of the battery or charging is. This is very confusing for
users who expect to be able to plug in a charger with the system
in suspend and see that it starts to charge.
Past platforms from this OEM have had two LEDs so this has not
been an issue.
BUG=chrome-os-partner:49151
BRANCH=glados
TEST=put chell in suspend, plug in charger to see amber LED and
then remove the charger and see that it blinks white again.
Change-Id: I60e849d7b8b717fb568d7d5d64046621c1c34157
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/332625
Reviewed-by: Shawn N <shawnn@chromium.org>
It turns out TRNG could turn idle under certain circumstances, and
needs to be restarted in that case. This code adds a check for the
idle state and necessary recovery.
BRANCH=none
BUG=b:27646393
TEST=none yet
Change-Id: Ibd0a13f40f5ce081d4211b2c0f1026468967f826
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/332573
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If we have already completed negotiation as a sink and
pd_send_request_msg() fails, issue a soft reset so we don't remain
indefinitely at our previously negotiated voltage.
BUG=chrome-os-partner:50346
BRANCH=glados
TEST=Manual on chell. Attach zinger to port 1, then attach zinger to
port 2. Verify that port 1 negotiated to 20V. Detach port 1 and verify
port 2 successfully negotiates to 20V and begins charging.
Change-Id: I4f8ff9a1e3ef49858f6ae5c3ccb5b5d4d847e2d1
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/332642
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
skylake.c does not make use of pause_in_s5 and related code, so
it will always has 10 second pause in POWER_S5 before transition
to POWER_S5G3, and this CONFIG flag is adding about 290 bytes of
unused code for host command and console command.
BUG=none
BRANCH=firmware-glados-7820.B
TEST=make buildall; system can shutdown and enter SOC-G3 properly
Change-Id: I1d507b925e13f794e9826a43ebdad898087a6663
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332025
Reviewed-by: Shawn N <shawnn@chromium.org>
After commit 237406c5b1, there is chance
that pd_power_supply_reset() will be called during S0->S3, and it
interrupts AP and fails suspend if we are using MKBP_EVENT.
This is because mkbp_send_event() does not check power state POWER_S0S3.
Modify the condition to check events when AP is not in S0.
BRANCH=none
BUG=chrome-os-partner:50833
TEST=powerd_dbus_suspend always works without being resumed
Change-Id: Id905a2cd4d2a0376bca163f40c68bcf4208d8bf5
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/331160
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Milton Chiang <milton.chiang@mediatek.com>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
- Send host commands to TCPCs based upon CONFIG_HOSTCMD_PD, since
boards with off-the-shelf TCPCs will also have a PDCMD task.
- Don't log VBUS voltage if we have no VBUS ADC channel.
BUG=chrome-os-partner:50819
BRANCH=None
TEST=`make buildall -j` with subsequent kevin board commit.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I33347402ec31e1754ad8e9a62814d5c1f345737d
Reviewed-on: https://chromium-review.googlesource.com/331343
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
CONFIG_SHI ("SPI host interface") has identical meaning to
CONFIG_HOSTCMD_SPS ("Accept EC host commands over the SPI slave"). Use
CONFIG_HOSTCMD_SPS, since it came first and is already defined in config.h.
BUG=chrome-os-partner:50819
BRANCH=None
TEST=`make buildall -j`
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I665c405ad72caa3b84e583a80c0893e4c625632a
Reviewed-on: https://chromium-review.googlesource.com/331342
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This change changes the full ADC range for VBUS to the correct value.
BUG=none
BRANCH=none
TEST=Verify VBUS voltage reported by `adc` matches measured voltage
on scope.
Change-Id: I3497ea790c4cbce66845d4cc661e1a0437c1cdfd
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/331283
Reviewed-by: Shawn N <shawnn@chromium.org>
reverse() swaps the endian-ness of a buffer of
specified length. This change moves the implementation
to a common location.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=compilation succeeds
Change-Id: If8c97f53cc199d63c1caebbd999e1c099814387e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331333
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
_cpri__GenerateKeyEcc, and _cpri__GetEphemeralEcc are expected to
set the size of the result in accordance with the curve being used.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py, test CPCTPM_TC2_2_14_02_05 passes
Change-Id: I558cc56f689c2d33c12876ddbfde7e9659613d2c
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331210
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
rev5 battery LED control was misplaced in wrong function.
Move it back to oak_led_set_battery().
BRANCH=none
BUG=chrome-os-partner:49375
TEST=ectool led battery [green red off] are correct
Change-Id: I83bc24c7ea7695be2a638e97b7db6e0c38840a16
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/330509
Reviewed-by: Rong Chang <rongchang@chromium.org>
We're supporting a wide range of batteries, and since file name
matching is based on HWID, we don't need to maintain a separate
table of supported HWIDs in our utility.
BUG=chrome-os-partner:49589,chrome-os-partner:50469
BRANCH=None
TEST=buildall
Change-Id: I3e7c62379c07a598e23f3c543959503d3d25aee3
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/330231
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Latest GCC gives compiler error:
util/iteflash.c: In function verify_flash:
util/iteflash.c:927:9: error: res may be used uninitialized in
this function [-Werror=maybe-uninitialized]
return res;
^
BUG=None
TEST=`make buildall -j` outside chroot
BRANCH=None
Change-Id: I184d8673020552797fd54bb98ee582a63debbf16
Signed-off-by: Anatol Pomozov <anatol.pomozov@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/330873
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT
variant to distinguish which verson ec is.
In config_chip.h, we use CHIP_VARIANT to specify the size and start address
of program memory. Ecst tool also needs a chip parameter to make sure
the address range checking of entry pointer won't fail.
Modified sources:
1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec
of npcx ec.
2. config_flash_layout.h: Replace constant value with
CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE.
3. build.mk: Add -chip parameter for ecst tool to check entry address.
4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/330072
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
