Ensure GPIOs are inputs when read: Initialize GPIO direction on startup,
and clean up register accesses using reg names rather than magic numbers.
Add board version reporting with CONFIG_BOARD_SPECIFIC_VERSION.
BUG=None
BRANCH=servo
TEST=version is correctly 3
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Ia04b01932fc36540af64b48b5e0bb6516f1529e2
Reviewed-on: https://chromium-review.googlesource.com/749693
Reviewed-by: Shawn N <shawnn@chromium.org>
Most boards had an identical implementation for this function,
previously known as board_is_consuming_full_charge(). To reduce copy
paste, let's just move it to common code. Boards that charge ramp
without a battery will have to define their own implementation, but
there probably won't be any boards like that in the near future.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: Ic99a378ac26dfd35d7d718bf9376eacfa8609166
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/748919
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Robo's LED spec is Red <= 5%, Orange 6 < SOC < 97, Green >=
97%. However, the table had Orange and Green flipped. This CL corrects
that error.
BUG=b:64192049
BRANCH=coral
TEST=Used EC console battfake command to verify that charge LED color
is red until 5%, then orange until 94%, and green after that. Note the
94% limit is due to the define CONFIG_BATTERY_LEVEL_NEAR_FULL which is
set to 94 as that's when the battery will want charging again after
reaching 100%.
Change-Id: Ia8395d6ca28ab000e12fb7a43f13721c7959e35d
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/748971
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support the ITE IT5205 Type-C USB alternate mode mux.
BRANCH=none
BUG=none
TEST=1. Successfully verify chip ID.
2. Verify set_mux() and get_mux() functions set and return
consistent values.
3. The mux control register setting as expected after set_mux().
Change-Id: I9ff066dc9e74683df1371b70290e2aeaa86cb96b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/741211
Reviewed-by: Shawn N <shawnn@chromium.org>
power_board_handle_host_sleep_event was added to allow boards like
poppy to enable/disable PMIC VR decay only once during S0ix
entry/exit. Now that the chipset hooks have been fixed, there is no
need of this board specific callback. If in the future, there is a
need to have such a callback, this change can be reverted.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that chipset suspend/resume hooks are called only once per S0ix
entry/exit, move the calls to enable/disable PMIC VR decay to
suspend/resume hooks.
BUG=None
BRANCH=None
TEST=Verified that PMIC VR decay enable/disable are called only once
during one S0ix entry/exit.
Change-Id: Ie01c083963efeacaf0092927f5778b7c1cebf74f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bump up port80 buffer size to 256.
BUG=None
BRANCH=None
TEST=Verified that all port80 messages from a boot-up or S3 resume are
present in port80 history buffer.
Change-Id: I76c95f308eaa30cc3789b93e59235a2dac0f632f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/747121
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The default behavior for this state is the charge color for 1 second
and then off for 3 seconds. The existing table entry for this state
was incorrect.
BUG=b:67759004
BRANCH=none
TEST=Verfied that in S3 state the pattern is 1 second charging color
followed by 3 seconds off.
Change-Id: I838cdb34a23cd9224761bd7f16a3a1d9cb980fd6
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/741076
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
1. Add a new config option to define history buffer length. This
allows boards to override this option if required.
2. Get rid of unused PORT80_POLL_PERIOD macro
BUG=None
BRANCH=None
TEST=Verified that all port80 messages from a boot-up or S3 resume are
present in port80 history buffer.
Change-Id: Ie64680459f58358713a1b1445a0b99fcfe1c1cdc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745902
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to
reinitialize S0ix flag, add a new default state
HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of
the code to take correct action depending upon the state that is
currently triggered.
BUG=None
BRANCH=None
TEST=Verified that SLP_S0# interrupt doesn't get asserted during
runtime S0ix.
Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a common hook handler on CHIPSET_RESUME to log port80 resume
message instead of duplicating the same code in all chip lpc_resume.
BUG=b:68669668
BRANCH=None
TEST=Verified that port80 resume is logged on S0ix and S3 resume.
Change-Id: I313692f5499717d0d8f62be2ba3b8566c46e4dde
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new LPC helper routine lpc_resume_clear_masks that can be used
to clear SCI, SMI and wake masks upon resume from S3. This is done to
mask the events until host explicitly unmasks them.
It also ensures that these masks do not get reset on resume from S0ix
where the host does not re-configure these masks.
BUG=b:68669668
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. On resume from S0ix, SCI mask is not reset.
3. On resume from S3, SCI mask is reset and then set again by host request.
Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745533
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Flashing STM32 requires the EC UART. The path of EC UART PTY was
originally set under some conditions which didn't reflect the case.
Instead of fixing these conditions, this change simply moves it
inside flash_stm32() as other flash functions don't need EC UART PTY.
BRANCH=none
BUG=b:67010776
TEST=Used servo-micro to flash_ec a STM32 EC, no error on getting EC
UART PTY.
Change-Id: I20c31de8e6c7a99fde259f4f397e53325ee80b07
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/745101
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Makes RW verification a little faster (268ms vs 294ms), at no
cost since RO still has enough space. Doesn't make any difference
in time to active USB, as USB enumeration is still the bottleneck.
BRANCH=none
BUG=b:35647963
TEST=Boot hammer, check that [0.267707 RW verify OK] is better
than without this patch ([0.294128 RW verify OK]).
Change-Id: I7d6564226616bfa807a636198d53ca7b2ea7081a
Signed-off-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-on: https://chromium-review.googlesource.com/744297
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The compass uses oversampling to produce accurate values.
MAX_ODR is functions of the repetitions setting.
80Hz is too high, calculate the frequency based on preset setting.
Currently, we use 'SPECIAL' that was calculated for Ryu.
BUG=b:68394559
BRANCH=eve,reef,poppy
TEST=Check with ectool motionsense info 3 the frequency is around 30Hz.
Before:
Min Frequency: 781 mHz
Max Frequency: 80000 mHz
After:
Min Frequency: 781 mHz
Max Frequency: 29579 mHz
Check with AIDA64 the compass is not stuck and return changing values.
Fixup of CL/570482
Change-Id: Idcfed1418f59e755e5647d018351c6a7397ffe1b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/742146
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This patch makes use of a recently introduced vendor command for
password control.
The new option '-P,password' is introduced to allow the device user to
set/clear the CCD password. Command line echo is suppressed when
password is being entered, so it is required to enter it twice.
To stay consistent with the 'ccd' Cr50 console command conventions the
word 'clear' should be used as the password when one wants to clear
the CCD password. All policies for setting/clearing the password are
the same as when setting it from the Cr50 console.
BRANCH=cr50
BUG=b:62537474
TEST=set and clear password when accessing over /dev/tpm0. Verified
that attempts to set/clear password over USB fail.
Change-Id: I7721d9ce12da8b7c89fc80eaa69cb8dd001abdb8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/741172
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
According npcx ec wake-up mechanism by espi VW events, the driver
needs to make sure the IE/WE bits in VWEVMSn and the VWUPD bit in
ESPIWE registers are both set. Or ec won't wakeup by VW signals until
the other wake-up events occured. (WE bit of VWEVMSn is introduced on
npcx7.)
In this CL, we turn on IE/WE bit in VWEVMSn registers during espi driver
initialization and toggle the bits of ESPIWE register for VW and general
events such as ESPI_RST and so on when ec turn on/off host interface's
interrupts to make sure ec can wake-up from deep idle by espi events in
time.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 5 hours and no symptom occurred on poppy.
Change-Id: I853532508bf9da5f3abc39e20ab848e659ca5e26
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/725559
Reviewed-by: Amit Maoz <amit.maoz@nuvoton.corp-partner.google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
In DEV, it's necessary to rollback to reenter prod signed
images. Let's make this reasonably easy.
BUG=None
BRANCH=cr50
TEST=CR50_DEV fw does roll back to prod..
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Id39c3e501782da3f088760ec27d09f1ffc7b7f58
Reviewed-on: https://chromium-review.googlesource.com/734840
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It is necessary to be able to set password both from the Cr50 console
and through a vendor command.
This patch moves all password management logic to the TPM task context
using the alternative vendor command path.
BRANCH=cr50
BUG=b:62537474
TEST=verified that using Cr50 console CCD password still can be set
and cleared as before.
Change-Id: I0574caf931e3717567fdb270e406643eac47764b
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/740914
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To protect zoombini's charge inductor, the input current limit needs to
be limited to 2.7A at voltages over 18V.
BUG=b:67020411
BRANCH=None
TEST=Flash zoombini; Verify that when charger voltage is over 18V, input
current limit is limited to 2.7A.
Change-Id: Ic0a790d3b5aa6bda52ba9c5f41e28a2c6fa9417c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/738920
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently, the only we init we need to do is mask VCCIO and 5VA from the
power good tree. Additionally, we deassert PMIC_EN for 30ms during
boot.
BUG=b:66000679, b:66975317, b:66952064
BRANCH=None
TEST=Flash zoombini; Verify that PMIC initializes okay.
Change-Id: I29a300247e4a2359b98d3546de7a024fd111958e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736313
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The 5V power good signal is being removed from the PMIC power good tree,
however, if the 5V power good is not asserted, we should not try booting
to S0. This is because the 1050_STG rail load switch is powered off of
the 5V rail.
Since wireless power control is being moved to the AP, these pins are now
repurposed to control the PMIC enable and for the 5V power good signal.
This commit adds the 5V power good pin to the EC and makes it a required
power signal for S0.
BUG=b:66000679
BRANCH=None
TEST=make -j buildall
TEST=flash zoombini; Verify EC boots up okay.
Change-Id: I8924320030a00b8808aea27fb668451e6e41d590
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736312
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If charge and discharge FETs are both disabled, then try reviving the
battery by sending 0x23a7 using manufacturer access. This is
required to get the battery out of emergency shutdown mode which is
entered upon hardware battery cut-off.
BUG=b:68044490
BRANCH=None
TEST=Verified that hardware and software based battery cut-off work as
expected. Device boots up fine on connecting AC power.
Change-Id: I1aed44c50e80b74b7b19c9808f465273bfd7b0da
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/738643
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
old_val may change value after cmpxchg, need to reset to 0 for next loop
comparison.
BUG=None
BRANCH=master
TEST=On Soraka modified for ISH board, running more than 4 hours sensor
data fetching by host command, and no problem.
Change-Id: I720230e196771071c8ba204458da6c4788d374ea
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/738914
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A built-in function (__builtin_ffs) is missing after we sync down
the source code to latest.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=We use the CL:730246 to verify this change, and
no error was received after running the test.
Change-Id: I5210f85db05650545c9924940e8b24e350b82f71
Reviewed-on: https://chromium-review.googlesource.com/730245
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Coral inherited from Reef a board.h modification of CC_DEFAULT which
disabled Events and the LPC channel. The LPC channel console prints
are required for the FAFT test firmware_ECBootTime
BUG=b:63488727
BRANCH=none
TEST=Tested with and without CC_LPC channel and verified that the FAFT
test firmware_ECBootTime pass/fail tracked accordingly.
Change-Id: I1e943978a4f23ee8f53e6951549f31c7231e463f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736679
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Also, fix uart_rx_available to only call
clock_refresh_console_in_use when the default pad is selected.
BRANCH=none
BUG=b:65526215
TEST=On Lux, EC console works, so does pad-switching EC-EC comm,
and idlestats shows that the EC goes to deep sleep.
TEST=In uart_alt_pad_write_read, increase usleep time in loop from
100 to 10000 (the shorter 100us time prevents EC from going
into deep sleep during the transaction), no transaction
error in EC-EC communication when system goes into deep sleep.
Change-Id: I3855b07f37def0ac9cfd700318ba64c432d3c42b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/735103
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Define NPCX_UART_* macros instead of having so many ifdef
NPCX_UART_MODULE2 in the code.
Also, do not set NPCX_WKEDG bit in npcx_uart2gpio: instead
set it in uart_config just just like NPCX7 does it.
BRANCH=none
BUG=b:65526215
TEST=On Lux, EC console works, so does pad-switching EC-EC comm.
TEST=Flash soraka, using "idlestats", check that EC goes into
deep sleep, and that it can be woken up typing in EC console.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I84b4f980fa79ed43640df4afc23cdc24cca21d99
Reviewed-on: https://chromium-review.googlesource.com/730029
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
NPCX5* only has one UART controller, which can be switched
between 2 pads. We keep the default pad for EC console,
however, we allow switching to the alternate pad for short,
infrequent, transactions. Both pads are assumed to use the
same baudrate and other line settings.
When switching pad, we first configure the new pad, then switch
off the old one, to avoid having no pad selected at a given time,
see b/65526215#c26.
Because of the added complexity of npcx_gpio2uart (and the fact
that it uses the global variable "pad" define in uart.c), we
move the implementation to uart.c (npcx_uart2gpio is also moved
for consistency).
When the pad is switched to alternate pad, characters input
and output on the EC console (default pad) would be lost. To
compensate for this, we:
- Switch back to main pad in case of EC panic, so that output
is shown on EC console.
- Immediately abort current alternate pad transaction if a
character is received on the default pad. Note, however,
that the first character will be lost (this can be worked
around by telling user to press enter, and have servod/FAFT
always send 2 blank lines (instead of just one) before
sending a command).
- Inhibit pad switching for 500ms after receiving a character
on default pad. Assuming a reasonable typing speed, this
should allow developers to type console commands relatively
comfortably, while not starving the alternate pad communication
for too long.
The logic above could be simplified significantly by implementing
software flow control (XON/XOFF, see b/67026316).
BRANCH=none
BUG=b:65526215
TEST=While follow-up CL that writes long 1k buffers, the following
works fine:
- type 'uart' in EC console
- Read battery power consumption from servod, which "types" in
the EC console:
while true; do dut-control ppvar_vbat_mw; sleep 1; done
no failure is seen.
TEST=Add this test code in uart_alt_pad_read_write, after the pad
has been switched, and check that panic information is
consistently printed correctly:
{
static int t;
if (t++ > 20)
t = t / ret;
}
Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659458
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This updater combines console and firmware update commands to
update both RO and RW sections of servo_v4 and servo_micro.
BRANCH=None
BUG=b:37513705
TEST=updated firmware
Change-Id: I9f585c90f5849f8dd7c9d2e08111ffbd5770fd54
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/668156
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The STM32F that we use doesn't support hibernate. This doesn't matter
much since stop mode uses very little power anyways.
BUG=b:67772394
BRANCH=none
TEST=check that the hibernate command is gone via help on the EC
console
Change-Id: I712b6b0ce1376357acf99f01b1c84fcce0642805
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/736815
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
There is a fundamental difference in host behavior w.r.t. S3 and
S0ix. When the host enters S3, it asserts the SLP_S3# signal until it
is woken back up. Thus, EC depends on the SLP_S3# signal state to
decide when to notify listeners about CHIPSET_SUSPEND and
CHIPSET_RESUME state.
With S0ix, SLP_S0# signal is asserted whenever host enters
S0ix. However, periodically (every 8 seconds), the host wakes up for
some bookkeeping activities, but does not come out of the low power
mode completely. This bookkeeping activity takes ~2-5 ms and the host
goes back into S0ix state. Because of this periodic activity, SLP_S0#
signal is de-asserted and asserted back every 8 seconds.
Thus, if the power state machine depends solely on the SLP_S0# signal
to notify CHIPSET_SUSPEND and CHIPSET_RESUME states, then all the
listeners would be performing unnecessary actions every 8
seconds. This leads to a number of side-effects including:
1. Dual-role toggle being enabled and disabled every 8 seconds.
2. Power spikes in EC power consumption during S0ix every 8 seconds.
In order to avoid the side-effects of periodic host activity in S0ix,
this change adds a new flag s0ix_notify, which is set based on the
notifications that are pending based on host sleep event.
On receiving host sleep event for S0ix suspend, s0ix_notify will be
set to S0IX_NOTIFY_SUSPEND. Next, whenever SLP_S0# is asserted,
power_state machine notifies listeners of CHIPSET_SUSPEND
and resets s0ix_notify flag to S0IX_NOTIFY_NONE. Thus, all future
assertions of SLP_S0# do not result in the suspend notification.
Similarly, on resume, power_state machine will not notify
CHIPSET_RESUME on SLP_S0# deassertion. Instead the host sleep event
for S0ix resume will set s0ix_notify flag to S0IX_NOTIFY_RESUME and
wake chipset task. The power state machine in turn will notify
listeners of the resume event and reset s0ix_notify flag.
BUG=b:65356050,b:67750352
BRANCH=None
TEST=Verified that the CHIPSET_SUSPEND/CHIPSET_RESUME notification
happens only once during a system suspend/resume cycle. Periodic host
wakes for book-keeping activities do not result in
CHIPSET_SUSPEND/CHIPSET_RESUME notifications.
Change-Id: Idf253b9393a0c25ff2eac63c60ddbcd3af954818
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/729478
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Implement the following required features in the USB PD Rev. 3.0
specification.
Not_supported control message: Inform a port partner that a
particular message is not supported.
Battery capabilities extended message: Report battery design
capacity and last full charge capacity.
Battery status data message: Report battery state of charge
Collision avoidance: New scheme to avoid collisions caused when both
source and sink want to send messages.
Cable communication: Only the VCONN source can communicate with the
cable plug. This is NOT implemented because although the drivers have
the capability of communicating with a cable plug, the PD stack doesn't
currently need to talk to a cable plug. This is okay since the current
PD design doesn't source or sink more than 3 amps and all Type-C cables
are required to be 3 amp capable.
BUG=b:64411727
BRANCH=None
TEST=`make -j buildall`
Passed relevant PD Rev 2.0 compliance tests
Successful PD negotiation with PD Rev 2.0 and 3.0 chargers
Tested with low power none PD charger.
Modified a Kevin to operate as a PD 3.0 charger and sent
all required messages and verified the return messages.
Also tested collision avoidance by verifying that a sink only
transmits when the source indicates it's okay.
Used Twinkie to verify that PD was operating as v3.0.
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: Ifd77e92ec4e9106236f9221393d2bfb97263d979
Reviewed-on: https://chromium-review.googlesource.com/603003
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch makes EC notify the host of BJ plug or unplug event
by triggering EC_HOST_EVENT_PD_MCU. The host can then use
EC_CMD_PD_HOST_EVENT_STATUS to get event details.
BUG=b:67060237
BRANCH=none
TEST=Boot Fizz on Type-C. Plug/unplug BJ adapter. Verify host event
is set by hostevent. Verify available_charge is set by hacking
chgsup command.
Change-Id: I1831bec9715e0191cb9610e05d08bbc08347b513
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/692848
Reviewed-by: Shawn N <shawnn@chromium.org>
TPM reset sequence when TPM wipeout is requested has a side effect of
rebooting the entire device. This is not always desirable, in some
cases other actions need to happen before the device is rebooted.
This patch makes resetting the EC the TPM reset caller's responsibility,
BRANCH=cr50
BUG=none
TEST=verified that RMA reset and WP disable properly wipe out the TPM
and reboot the device.
Change-Id: I6e827ce923a2454ae5b2e2597d1a4c9390bbb8b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/733813
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
When RMA process has been initialized and the user entered the
expected authentication code value, the Cr50 needs to wipe out TPM
memory, open and unlock CCD and reboot the device.
This patch adds a function to accomplish that. User response is
validated on the TPM task context, and TPM reset request also requires
TPM task processing. To decouple response processing from the
following reset, the response processing is handled by a hook task
callback, delayed for 1s to make sure that user receives the response.
After TPM has successfully reset the CCD is reinitialized with RMA
'opened' and the device is rebooted.
Just in case something goes wrong with the unlock and the hook is not
invoked, add a 10s deferred function to take the EC out of reset so
that the device still can reboot.
BRANCH=none
BUG=b:67007905
TEST=on a Bob device:
- on the Cr50 console enter 'ccd lock', verify that ccd is locked
(by examining output of the 'ccd' command)
- at the bash prompt enter gsctool -r -s -t, copy the
authentication code from the Cr50 console and pass it to gsctool.
- observe the device reset TPM wiping out its memory, enable CCD
and reboot.
Change-Id: I6fafb5e642cb2b6f2040507a7f1989607fd31316
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/729983
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
keyboard/button init are responsible for checking if user requested
manual recovery. However, by this time, hook init is not run and hence
host event set operation for manual recovery is dropped. This change
adds a call to lpc_init_mask before keyboard/button init operations
are performed.
BUG=b:68189465
BRANCH=None
TEST=Verified that manual recovery works fine. Recovery using software
command works too:
reboot ap-off
hostevent set 0x4000
powerb
Change-Id: I15cb648d4b253a523293c7ab2cd3e8e08e31a763
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/735799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Select optimal PDOs from the charger at various discrete voltage limits
and advertise them all to the DUT, in case the DUT does not support the
"best" > 5V PDO due to voltage limits.
BUG=chromium:776809
BRANCH=servo
TEST=On {samus, scarlet, kevin}, with zinger attached to DUT port,
verify DUT + CHG negotiate to max supported voltage. On 'black' servo_v4
board, verify scarlet negotiates to 12V.
Change-Id: Iea174e4f6bc303d561e28281b9ff20afb3073c25
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/730877
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
