Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8971
TEST=manual
waitms 1500
(see watchdog trace)
waitms 1500
(should see watchdog trace again)
waitms 3000
(should see trace, then system should reboot)
Change-Id: Ieb5009d7a7bc9e1ed795e58efb0cb44a1eeb2706
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8967
TEST=manual
While ssh'd into the device:
1) Create a test image:
Extracting to: /tmp/ecup
132+1 records in
132+1 records out
136132 bytes (136 kB) copied, 0.000550122 s, 247 MB/s
2) Force the EC into its RO image:
done.
3) Erase the A and B images, then reprogram them:
Erasing 163840 bytes at offset 81920...
done.
Reading 136132 bytes from /home/chronos/user/ecb.bin...
Writing to offset 81920...
done.
4) Repeat step 3 about 10 times while monitoring the EC debug console.
Commands should complete successfully all the time. (Note that during
the flashwrite, there's a ton of debug output; what you should NOT see
is something like this:
WATCHDOG PC=00002104 / LR=0000597f / pSP=200013a0
Change-Id: I2f1f05eb19abcd6e19c6364f6d4ac785cca6a4c6
Provide the required plumbing for the stm32 keyboard scan code so that
the message layer will pick up keyboard scans.
The design is as follows:
- When a change in keyboard state is detected, the keyboard matrix
scanning code will call the board-specific board_keyboard_scan_ready()
function to interrupt the AP.
- The AP will initiate a CMDC_KEY_STATE transaction over SPI or I2C
- The SPI or I2C driver will call message_process_cmd() to process the
command
- This in turn will call keyboard_get_scan() to get the latest scan data
For SPI:
- The AP will initiate an 20-byte (or longer) SPI transaction
- The EC will see the command, and provide the keyboard state in response,
with the response being part of the same transaction
For I2C:
- The AP will initiate a 1-byte write to set the EC mode.
- The AP will then initiate an 18-byte read, and the EC will send the
message including keyboard state
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: I905ef9d567e43d85fb851052f67586eff58e1167
Signed-off-by: Simon Glass <sjg@chromium.org>
Add some basic functions to start DMA operations for transmit and
receive.
BUG=chromium-os:28925
TEST=build on daisy and discovery; run on daisy
Change-Id: Ifceeed2af80cf5f00e1ce1a49b1139a76585b0bf
Signed-off-by: Simon Glass <sjg@chromium.org>
Now Link has 256kB parts, we can restore the third partition and use 80kB partitions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Link proto-1, try to use RO/A/B images (sysjump B, then boot).
Change-Id: I9b7e4cae1504e86a62643db4d035cc9f3de0af52
(cherry picked from commit cefaf59328e4b91308d0347cc1f55861e93db480)
Add nopll command to turn off the PLL, reducing the system clock to 16Mhz.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8798
TEST=manual
boot system
press power button to boot x86
temps // should print all temperatures
timerinfo
timerinfo
timerinfo // convince yourself this is counting up at about 1MHz
nopll // this drops the system clock to 16MHz
temps // should still print all temperatures
timerinfo
timerinfo
timerinfo // should still be counting up at about 1MHz
Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
Add a host command returning chip information. The interface is in common/
while the implementations are in chip-specific code (note: added simple
value for stm).
BUG=chrome-os-partner:8567
TEST=on board
% ectool chipinfo
Chip info:
vendor: xx
name: yyyy
revision: zzzzz
Change-Id: I5030a03a6fcfbfc080d5acd8efb763fde7eefde5
This has been useful for me to be able to test lid behavior remotely
since it is not available via servo.
This also has a minor change to send a task message after sending
the power button pulse so the state machine behaves properly.
BUG=none
TEST=Execute 'lidclose' and 'lidopen' commands via ec uart and
see the appropriate events set and wake behavior when the system
is off. With a (not yet published) coreboot I am able to handle
lid close events to enter suspend.
Change-Id: Iec1c68121d42b66305ba5dfd20e81453538a97e2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
The SCI pin is not connected to a GPIO and it uses a different
method to trigger a pulse via LPC0SCI.
The ACPI specification requires SCI for 3 conditions:
- SCI event pending
- Input Buffer Empty
- Output Buffer Full
The buffer full/empty SCIs are used to nudge the kernel driver
along so it does not have to poll for a potential slow EC to
be ready. This only really makes sense for the kernel channel
so they are only generated there.
BUG=chrome-os-partner:8277
TEST=using (unreleased) coreboot BIOS to test that the kernel
can receive SCI events and the ACPI method is successfully run.
Change-Id: I6b3717fcad6569bda4482d9aaa37d45b4cf36335
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7461
TEST=manual
make BOARD={bds,link,daisy}
make tests
flash link system and make sure it boots
Change-Id: I1241a1895c083e387e38ddab01ac346ca4474eb9
On Power+ESC -> ignore the power button being down until it's
released; system stays powered down.
On Power+ESC+Refresh -> send a power button pulse to the PCH. Ignore
the power button until after both the pulse has finished and the power
button is released.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8723
TEST=manual
Reboot system.
Press power.
System powers on normally.
Hold down ESC, tap power very quickly.
System resets and stays off.
Hold down ESC and power for several seconds.
System resets and stays off.
Hold down ESC and refresh and tap power very quickly.
System powers on; EC console indicates it's in RO.
Hold down ESC and refresh and press power for ~100ms
System powers on; EC console indicates it's in RO.
Hold down ESC and refresh and press power for several seconds.
System powers on; EC console indicates it's in RO.
Hold down ESC and refresh and press power for at least 10 seconds.
System powers on; EC console indicates it's in RO.
Change-Id: Idf9619da54ab299b0c65e6d68abb5e35e2ce9c79
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8573
TEST=manual
1) Hold down refresh key and type 'reboot' from EC console. Console
should not show "[KB recovery key pressed at init!]"
2) Press power+esc+refresh. Console SHOULD show the message.
3) Press power+esc. Console should NOT show the message.
Change-Id: I642a7667b81c8d90c9490b23ce0f3519364427e4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8724
TEST=if timestamps show up in the debug output, it works
Change-Id: I5264a3a40a07a824cc15b39a7bd81f2db02a3c13
After commit 84a286b1, the watchdog handler was no longer properly
connected to the interrupt vector.
Also add a couple of flushes to get all the traces.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8721
TEST=type "waitms 5000" in the EC console to trigger the watchdog and
check we get the right serial trace.
Change-Id: I5a4dcdbc9000e7caeb5361d196c1f737a477c353
This uses the last bank of flash to hold persistent settings, and
looks at the write protect GPIO to decide whether to protect the chip
at boot (chrome-os-partner:7453).
For ease of debugging, I've temporarily hacked this so flash uses the
RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead
of the write protect signal; this works around chrome-os-partner:8580.
Also note that if you write protect any blocks even temporarily,
you'll need to do a power-on reset to clear them before you can
reprogram the flash. See chrome-os-partner:8632. At the EC console,
"hibernate 1" will do that, or you can just yank the power.
This also fixes a bug in the flash write and erase commands, where
they weren't properly detecting failure if you attempted to modify a
protected block (missed an interrupt reason...)
New "flashwp" console commands work. LPC commands need reworking.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8448
TEST=manual
Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
No point in saying "edit the file if it doesn't work", when we could just
provide a slow version instead.
BUG=none
TEST=none
Change-Id: I94731495635e4dc6d0aa6e3f577cb727af92894a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Now that we can jump directly to other images, we don't need this.
We jump to image A by default, unless the recovery button or signal is asserted.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8562
TEST=manual
Reboot -> runs image A
Reboot with reload (F3) held down -> runs RO
Reboot with 'dut-control goog_rec_mode:on' -> runs RO
Change-Id: I8259fe0d738ce0ca897d2f4427d8cf61858b8901
This is necessary at init-time for verified boot to jump from RO to
one of the RW images.
It's also used by factory EC update to update one image and then jump
to the updated image to finish the update. In this case, the x86 does
NOT reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8449
TEST=manual
1) power on x86 and log in
2) sysjump a --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted
Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
More modules can be disabled individually through CONFIG_ defines.
Reordered early module pre-init and init, and added comments to
explain why things are ordered in main() the way they are.
Fixed a few assorted init-related bugs along the way, like st32m
keyboard scan double-initializing.
BUG=none
TEST=build link, bds, daisy
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Allow to build without the power button task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: Ibc757a6641f195f0d10e6a673792b996694f8cec
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Remove dummy boot-time output to UART1; no longer needed now that
there's a debug command to do the same thing.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
comxtest - prints default message to x86 UART
comxtext ccc123 - prints 'ccc123' to x86 UART
Change-Id: I37d37aeca06bf71b106f5ad3473a79780fd089a9
Not compiled into any target; new version of temp_sensor.c is in common/
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=build link and bds
Change-Id: I00232a7cd8a8a9ee6353c5f04c86fcacc83cbd3e
For debugging PCH reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then use x86reset to reset it. Should see line state changes printed.
Change-Id: Ief2f09bd0986339812183d0b32dc0208437d1103
Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
And faninfo now checks if the fan is powered.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
1) faninfo --> fan is initially disabled and powered off
3) gpioset enable_vs 1 --> fan is now powered on, but still disabled
2) fanset 8000 --> fan is now enabled, and you should hear it
Change-Id: I97f35a20022cabd4520522f2d18ecb7603faabd1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
Also prints the current timer value when inits are done, and when the
watchdog task first gets to run (after all higher priority tasks sleep
at least once).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I342f86ad087fd18ab064a10a5bcdd0b69ee373d0
Implement a generalized I2C transmit-receive function that
write-then-read blocks of raw data. Original 8-bit and 16-bit
read/write functions are refactored.
SMBus read-block protocol for ASCII string is also implemented
based on this API.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8026,8316
TEST=manual:
Type 'lightsaber' to check 8-bit read/write.
Type 'charger' to check 16-bit read.
Type 'charger input 4032' to check 16-bit write.
Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Note that this only handles lid and power button; see
crosbug.com/p/8325 for write protect.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8185
TEST=manual
1. Check state with lid open
localhost ~ # ectool switches
Current switches: 0x01
Lid switch: OPEN
Power button: UP
Write protect: ENABLED
2. Press power button
localhost ~ # ectool switches
Current switches: 0x03
Lid switch: OPEN
Power button: DOWN
Write protect: ENABLED
3. Release power button and close lid
localhost ~ # ectool switches
Current switches: 0x00
Lid switch: CLOSED
Power button: UP
Write protect: ENABLED
Change-Id: I25f2fa3dfeac004dde9b10a4243ee235875f1b6e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8324
TEST=manual
1. When system is off, open lid. Debug console should show PB PCH pwrbtn activity.
2. Wait for system to boot.
3. Quickly close and open lid. Debug console should not show pwrbtn activity.
Change-Id: Ia018ff06a31ac2a68f20021d17e47ddb06096eb8
(Also define other host events)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8308
TEST=manual:
Use magnet to trigger lid-closed and lid-open.
'hostevent' should show raw events = 0x3.
Press power button.
'hostevent' should now show raw events = 0x7.
Change-Id: I9c8367d5152d526299a7a3149250de84cc2e0557
implement actual_key_masks[]. A ghost key exists if two columns share
more than one row (after ANDed actual_key_masks[]).
BUG=chrome-os-partner:7485
TEST=on bds. test cases:
single press of all keys.
~ 1 4 5: later 2 keys should be ignored (ghost).
h j k: all keys should work.
u R-shift 0 P: p should be ignored (ghost).
i R-shift ' p: P should show up.
Change-Id: I1ac105874a5327e839a5240ccbdd6304637ad404
We used to have flaky PECI temperature read so we ignored failure. Now
the PECI temperature read seems to work fine so we should have it report
error on failure.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7493
TEST=When powered off, 'temps' shows error on PECI temperature reading.
Change-Id: I161a8f84f66ba06959c21838ee364b2f8d8b4945
This is necessary to support SCI/SMI events.
Note that this breaks compatibility with previous ectool builds - and
probably also breaks flashrom support.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8253
TEST='ectool hello' and 'ectool flashinfo' still work
and 'ectool usbchargemode 3 1' fails with error 2
Change-Id: If39e5b6e7cdcec1b5ec765594e8492925b430b10
Add console command 'autofan' to turn on automatic fan speed control.
Also modify 'fanset' to disable automatic control before setting fan
speed.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manual test
Change-Id: I2db85ce2e754bba21567b2c92e4476049d517627
On the STM32L UART without a FIFO, the Transmit Register might need
some time before pushing its content to the shift register.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on ADV board, verify we are no longer missing most of the carriage
return on console.
Change-Id: Ic638dc452d6e30a5f127710fc964143d477fa1d6
