CR50 will need three serial endpoints for the streaming AP and EC UART
and exporting its own console through USB. This change adds a macro to
create endpoints that can be recognized by the usb_serial driver.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=Verify "/dev/google/Cr50*/serial/Blob" prints capital letters when
lower case letters are input.
Change-Id: Iddf2c957a00dc3cd5448a6a00de2cf61ef5dd84c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336441
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This adds (and uses) some additional flags for gpio.inc's
PINMUX() macro, to configure specific pads as wake sources when
the SoC is sleeping.
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
The sleep/deep sleep behavior is unchanged. This just replaces
hard-coded wake sources with pads configured in gpio.inc and the
chip/g/sps.c module. Tests from previous CLs still pass.
Change-Id: I6608dc959524f42fd589feb804fa06f29cfd9b9c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336838
Reviewed-by: Dominic Rizzo <domrizzo@google.com>
modify g781.c/.h to g78x.c/.h to suppor both G781/G782 temp sensor
based on CONFIG_TEMP_SENSOR_G781 or CONFIG_TEMP_SENSOR_G782
BUG=none
BRANCH=none
TEST=make buildall; able to get temperature data on board with G782
Change-Id: Ia32c85e9964bfd7c0c5263f04368bc001a27fe10
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/334228
Reviewed-by: Shawn N <shawnn@chromium.org>
After a charger is attached, we may set a charge limit based upon BC1.2
or USB-C Rp before PD negotiation completes. Therefore, allow 2 seconds
for all negotiation to complete. Previously this behavior was implicit
when using SW charge ramp.
BUG=chrome-os-partner:51280
BRANCH=glados
TEST=Manual on chell. Insert stock charger, verify that it is detected
as TYPE_UNKNOWN until timeout.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I52f02de46fa92b66a9fbaddb94a062310688f028
Reviewed-on: https://chromium-review.googlesource.com/334312
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is keyboard test mechanism request for "multiple key press test",
we can thru the testing to scan out kso ksi pins shortting or keyboard has
multiple key pressing, below was the testing steps:
1. Turn off internal keyboard scan function.
2. Set all scan & sense pins to input and internal push up.
3. Set start one pin to output low.
4. check other pins status if any sense low level.
5. repeat step 3~4 for all keyboard KSO/KSI pins.
6. Turn on internal keyboard scan function.
BUG=chrome-os-partner:49235
BRANCH=ToT
TEST=manual
Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed.
if no pins short together, it shows passed.
Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/332322
Reviewed-by: Shawn N <shawnn@chromium.org>
cr50 has three UARTs that it will be using. This change modifies the
uart api to specify which uart to use.
BUG=chrome-os-partner:50702
BRANCH=none
TEST=change the interrupts and CONFIG_UART_CONSOLE to see that the
different UARTs can be used.
Change-Id: I754a69159103b48bc3f2f8ab1b9c8b86cea6bea5
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/333402
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
NULL padding (aka vanilla RSA) support is required by
the TPM2 test suite (referred to as TPM_ALG_NULL in the
tpm2 source).
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2 pass
Change-Id: I9848fad3b44add05a04810ecd178fbad20ae92cc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/328830
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
This just adds the framework to use for implementing sleep and
deep-sleep. This provides a custom idle task, and a new "idle"
console command to control what that task should do (nothing,
yet).
BUG=chrome-os-partner:49955
BRANCH=none
TEST=make buildall; test on Cr50
Other than the new idle command which does nothing, there is no
visible change. This is just a stub.
Change-Id: I8a9b82ca68dd6d1e3e7275f4f6753a23a7448f1d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/336420
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update the GPIO mapping based on the Kevin P0 schematic and drive the EC
and AP select signals low.
BUG=chrome-os-partner:50728
BRANCH=none
TEST=test that DIOB2 and B3 default to low, but can be set high or low.
Change-Id: If574436913ad0271540bcce2939fe1f4574dae97
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/335381
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This config option allowed us to disable the TPM protocol on the
SPI slave bus and replace it with our EC-style host command
protocol. We only used this for early testing and don't need it
anymore, so we can get rid of it completely for this SoC.
BUG=none
BRANCH=none
TEST=make buildall; test on cr50
Change-Id: I2126537e8bcc78e583cf426a3a83962c9ff1a121
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/334762
Reviewed-by: Scott Collyer <scollyer@chromium.org>
On oak battery, when the battery is dead it reports 0 for desired
voltage, current, and state of charge. In this case we should allow
charging.
Added a CONFIG option for this that should be removed as soon as
the battery side is fixed.
With this CL, when a dead oak battery is used and a charger is
connected, we attempt to charge it.
BUG=chrome-os-partner:51454
BRANCH=none
TEST=test on an oak with a dead battery. w/o this CL, the battery
never charges because the charging not allowed flag is set. With this
CL, the battery charges.
Change-Id: If9f1250cd41aec265838e1d109f53c1bcd58c111
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/334471
Reviewed-by: Rong Chang <rongchang@chromium.org>
1. Always use wake-up control interrupt for keyboard KSI. This can also
wake-up EC from deep doze / sleep mode.
2. In keyboard ISR, we just clear interrupt status to prevent keyboard
interrupt can't be re-enabled.
(for example, a KSI interrupt wakes up keyboard scan task,
but keyboard_raw_read_rows() got 0.)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=keyboard function is normally.
Change-Id: If8c292189c6133b179a63dedcb7a18abbc091312
Reviewed-on: https://chromium-review.googlesource.com/333865
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Update flash_ec to allow flashing servo_micro
* Add servo_micro build
BUG=chromium:571477
BRANCH=None
TEST=updated servod is able to control gpio, gpio extender,
SPI flash, ec uart, ap uart on test yoshi
Signed-off-by: Nick Sanders <nsanders@google.com>
Change-Id: I4d69c83ae581cb41da928a27c39b7152475d7ca8
Reviewed-on: https://chromium-review.googlesource.com/327214
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
CONFIG_PMIC_FW_LONG_PRESS_TIMER was ported long time ago from
Tegra, but the codes are actually not used and erroneous.
It might wrongly trigger set_pmic_pwron(0), and turn off
PMIC power accidentally. This causes POWER_GOOD lost and
power state will go back to S5 during boot up.
Clean up the codes by referencing check_for_power_off_event()
of Rockchip.
BRANCH=none
BUG=none
TEST=bootup and press power button quickly right after we are in S0.
Bootup should still complete normally.
Change-Id: Ie034efa3575dbebae4debb1afc206fddd9116350
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/332724
Reviewed-by: Rong Chang <rongchang@chromium.org>
Increase LED blink cycle time to reduce power consumption on Oak rev5
with GlaDOS ID.
BUG=chrome-os-partner:50317
TEST=`make EXTRA_CFLAGS=-DBOARD_REV=5 BOARD=oak -j`
Change-Id: Ic00512434965471a82b94ef431e0ec88c9e4c0c3
Reviewed-on: https://chromium-review.googlesource.com/332346
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Currently when in suspend the LED blinks white no matter what the
state of the battery or charging is. This is very confusing for
users who expect to be able to plug in a charger with the system
in suspend and see that it starts to charge.
Past platforms from this OEM have had two LEDs so this has not
been an issue.
BUG=chrome-os-partner:49151
BRANCH=glados
TEST=put chell in suspend, plug in charger to see amber LED and
then remove the charger and see that it blinks white again.
Change-Id: I60e849d7b8b717fb568d7d5d64046621c1c34157
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/332625
Reviewed-by: Shawn N <shawnn@chromium.org>
skylake.c does not make use of pause_in_s5 and related code, so
it will always has 10 second pause in POWER_S5 before transition
to POWER_S5G3, and this CONFIG flag is adding about 290 bytes of
unused code for host command and console command.
BUG=none
BRANCH=firmware-glados-7820.B
TEST=make buildall; system can shutdown and enter SOC-G3 properly
Change-Id: I1d507b925e13f794e9826a43ebdad898087a6663
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332025
Reviewed-by: Shawn N <shawnn@chromium.org>
CONFIG_SHI ("SPI host interface") has identical meaning to
CONFIG_HOSTCMD_SPS ("Accept EC host commands over the SPI slave"). Use
CONFIG_HOSTCMD_SPS, since it came first and is already defined in config.h.
BUG=chrome-os-partner:50819
BRANCH=None
TEST=`make buildall -j`
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I665c405ad72caa3b84e583a80c0893e4c625632a
Reviewed-on: https://chromium-review.googlesource.com/331342
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This change changes the full ADC range for VBUS to the correct value.
BUG=none
BRANCH=none
TEST=Verify VBUS voltage reported by `adc` matches measured voltage
on scope.
Change-Id: I3497ea790c4cbce66845d4cc661e1a0437c1cdfd
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/331283
Reviewed-by: Shawn N <shawnn@chromium.org>
_cpri__GenerateKeyEcc, and _cpri__GetEphemeralEcc are expected to
set the size of the result in accordance with the curve being used.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py, test CPCTPM_TC2_2_14_02_05 passes
Change-Id: I558cc56f689c2d33c12876ddbfde7e9659613d2c
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/331210
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
rev5 battery LED control was misplaced in wrong function.
Move it back to oak_led_set_battery().
BRANCH=none
BUG=chrome-os-partner:49375
TEST=ectool led battery [green red off] are correct
Change-Id: I83bc24c7ea7695be2a638e97b7db6e0c38840a16
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/330509
Reviewed-by: Rong Chang <rongchang@chromium.org>
In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT
variant to distinguish which verson ec is.
In config_chip.h, we use CHIP_VARIANT to specify the size and start address
of program memory. Ecst tool also needs a chip parameter to make sure
the address range checking of entry pointer won't fail.
Modified sources:
1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec
of npcx ec.
2. config_flash_layout.h: Replace constant value with
CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE.
3. build.mk: Add -chip parameter for ecst tool to check entry address.
4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/330072
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add 1.8V IO support for some GPIOs and I2C pins. We use a array
(gpio_lvol_table) to confine which IO pins can switch to 1.8V. Before
setting it to support low voltage level, FW should set IO pin's type to
open-drain and disable internal pulling up or down.
We also add examples in gpio.inc of npcx_evb and npcx_evb_arm to indicate
how to set GPIO & I2C pins to 1.8V if user adds CONFIG_TEST_1P8V definition
in board.h.
In i2c.c driver, this version removes the internal pull-up feature of
i2c ports since the driving force is too weak. (about 30K ohm)
Modified sources:
1. gpio.c: Add 1.8V IO support for some GPIOs and I2C pins.
2. i2c.c: Remove internal pull-ups feature for i2c pins and move 1.8V
support to gpio.c.
3. register.h: Modified NPCX_LV_GPIO_CTL register & bits definitions.
4. npcx_evb\gpio.inc: Add examples of 1.8V IO.
5. npcx_evb_arm\gpio.inc: Add examples of 1.8V IO.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I73a840ae321820212e50d609dab17576117a7d64
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/330037
Reviewed-by: Shawn N <shawnn@chromium.org>
The base accelerometer on oak rev5 needs to be rotated 180 degrees
along the z-axis to match the standard reference frame.
BUG=chrome-os-partner:50312
BRANCH=none
TEST=manually rotate my oak rev5 and verify that `ectool motionsense`
reports correct accelerometer readings
Change-Id: I05a377b5f0827e2aad47d388dc3264d451580989
Signed-off-by: Ricky Liang <jcliang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/330484
Reviewed-by: Rong Chang <rongchang@chromium.org>
The default target hardware is rev5. This is a maintainess change for
old and deprecated HW.
BRANCH=none
BUG=chrome-os-partner:49114
BUG=chrome-os-partner:50720
TEST=manual
for N=1,5 do
make BOARD=oak clean && make BOARD=oak EXTRA_CFLAGS="-DBOARD_REV=$N" -j
Signed-off-by: Rong chang <rongchang@chromium.org>
Change-Id: Ibb4ebf9fab429964ace7c3e548598f0fb08e7dea
Reviewed-on: https://chromium-review.googlesource.com/330065
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
This change enables lid angle update that turns off keyboard scan in
tablet mode.
BRANCH=none
BUG=chrome-os-partner:49114
TEST=make BOARD=oak runtests
make BOARD=oak -j && make BOARD=oak_pd -j
load on oak and boot to vt2 console.
flip lid to disable range, type keyboard and check.
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: Ibd2f0d6ae33a95380c9fc52a7568166a04c119e9
Reviewed-on: https://chromium-review.googlesource.com/328884
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Previously the keyboard row and column pins could not use the GPIO
alternate function mechanism because their DEVALT bits were inverted
with respect to all of the others, making it impossible to correctly
configure them. With the refactor of the GPIO driver we can now add
the keyboard DEVALT entries to the gpio_alt_table, and use the
ALTERNATE macro and associated APIs to control the keyboard pin states.
The Wheatley RO firmware image is still 320 bytes smaller than before
the GPIO refactor.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Ran on Wheatley, manually verified keyboard functionality
Change-Id: Id04bc010834b5d95050b03ace6b0e1c5690757bf
Reviewed-on: https://chromium-review.googlesource.com/329762
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
1. Muxer of USB C1 port changes to Parade PS8740.
2. Add control of DP switch TS3USB3000RSER, using for switch DP to port 0/1
(same as rev2).
3. LED control logic is same as rev2.
4. Updates GPIO setting for rev5 pinouts.
BUG=chrome-os-partner:49375
BRANCH=none
TEST=build -j buildall tests
Change-Id: Ifc45ac30be8d46caa1cdb032ccce7569e5a14b99
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/321024
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
refer to commit d341615383,
adds the base accelerometer as well as the gyroscope to the list of
motion sensors on the board, connect with SPI bus. They are currently
wrapped behind an ifdef for HAS_TASK_MOTIONSENSE and OAK_REV5.
BUG=chrome-os-partner:50312
BRANCH=none
TEST=Build Oak EC with driver enabled and verify that we can calcuate
a valid lid angle.
TEST=Verify that signs of accelerometer conform to those shown in the
Chrome/Android/HTML5 doc/spec. See description in accelerometer_types.h
TEST=Verify that signs of gyroscope conform to those shown in the
"Sysfs interface to EC accelerometers" document.
TEST=make buildall tests
Change-Id: I4d900bc6bd7329db6ea53660fae86e5e2bbe9028
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/319295
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
refer to commit 574c806571,
adds the lid accelerometer to the list of motion sensors on the rev5.
Since commit bc404c94b4,
math_util.c is no longer to include "math.h" header file.
BUG=chrome-os-partner:50312
BRANCH=none
TEST=Build Oak EC with driver enabled and verify that valid
accelerometer data is read, and that range, resolution, and odr can all
be modified.
TEST=Verified that signs of accelerometer data conform to those shown in
the doc.
TEST=make buildall tests
Change-Id: I8df1b2331a1fbea82015b97985541e2ebc393d10
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/319332
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Except for the console UART TX and the SPI slave MISO, this CL
configures all the formerly output GPIOs as inputs. The Cr50
firmware at this point doesn't actually DO anything useful with
the GPIOs that would normally be outputs on the Kevin board (we
don't assert SYS_RESET, or EC_FLASH_SELECT, for example), and the
board *should* be designed so that no important signals like
those just float.
By using this configuration, we're trying to limit the potential
harm done by unexpected schematic changes. Once the system boots,
we should be able to use the SPI bus to update Cr50 to add more
features, such as testing Cr50 GPIOs individually.
BUG=chrome-os-partner:49952
BRANCH=none
TEST=make buildall, run on Cr50 board
Change-Id: I1f0a164e2cd3e4f632b862e33dba69f0dc944322
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329557
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The new signer command line option should be used by some boards, not
all of them. Add it for cr50 for now.
BRANCH=none
BUG=none
TEST=verified that --cros is added to the command line when cr50 blobs
are signed, and that the signed blob boots fine on b1.
Change-Id: Ibc38cc6233b57838129ae7d554921c1bae0e6b8c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329595
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
BUG=chrome-os-partner:49952
BRANCH=none
TEST=make buildall, run on Cr50 board
It's kind of hard to test GPIOs that aren't attached to anything,
but I've examined all the PINMUX controls and ARM GPIO settings,
and I *think* they're right.
Change-Id: I66ae94118f73c41193c6ca5c0af9708f6cc8a3e8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329526
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
