After a charger is attached, we may set a charge limit based upon BC1.2
or USB-C Rp before PD negotiation completes. Therefore, allow 2 seconds
for all negotiation to complete. Previously this behavior was implicit
when using SW charge ramp.
BUG=chrome-os-partner:51280
BRANCH=glados
TEST=Manual on chell. Insert stock charger, verify that it is detected
as TYPE_UNKNOWN until timeout.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I52f02de46fa92b66a9fbaddb94a062310688f028
Reviewed-on: https://chromium-review.googlesource.com/334312
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is keyboard test mechanism request for "multiple key press test",
we can thru the testing to scan out kso ksi pins shortting or keyboard has
multiple key pressing, below was the testing steps:
1. Turn off internal keyboard scan function.
2. Set all scan & sense pins to input and internal push up.
3. Set start one pin to output low.
4. check other pins status if any sense low level.
5. repeat step 3~4 for all keyboard KSO/KSI pins.
6. Turn on internal keyboard scan function.
BUG=chrome-os-partner:49235
BRANCH=ToT
TEST=manual
Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed.
if no pins short together, it shows passed.
Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/332322
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently when in suspend the LED blinks white no matter what the
state of the battery or charging is. This is very confusing for
users who expect to be able to plug in a charger with the system
in suspend and see that it starts to charge.
Past platforms from this OEM have had two LEDs so this has not
been an issue.
BUG=chrome-os-partner:49151
BRANCH=glados
TEST=put chell in suspend, plug in charger to see amber LED and
then remove the charger and see that it blinks white again.
Change-Id: I60e849d7b8b717fb568d7d5d64046621c1c34157
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/332625
Reviewed-by: Shawn N <shawnn@chromium.org>
With commit e9883124ff, a GPIO_INT macro was added. That change
also required that all instances of GPIO_INT in a board's
gpio.inc file come before any GPIO macros, or the interrupt
handler wouldn't work properly.
This CL just adds a warning comment about requirement to all
gpio.inc files.
BUG=chromium:471331
BRANCH=none
TEST=make buildall, test image on Cr50
This is a change to comments only. There is no new behavior to
verify, although I did run try out one new image just to be sure
nothing stupid happened.
Change-Id: I83f7819929a53bce3a8bae04d15b3ee3bda11738
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329334
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Previously these were often done in board.c files, which made it
impossible to include the gpio.inc anywhere else. As part of
refactoring the GPIO code we now need to be able to include gpio.inc
from common/gpio.c. Moving these defines into gpio.inc makes them
available wherever gpio.inc is included.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I28e7b5a1d40b113ae824b18f020b2d1e51e0c08a
Reviewed-on: https://chromium-review.googlesource.com/328822
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
EC boot / hash computing can be a bottleneck for system boot time.
Reduce this bottleneck by running our processor at 48 MHz through boot,
until vboot hashing of RW completes.
BUG=chrome-os-partner:49583
TEST=Boot chell, verify vboot hash completes within 1 sec of EC boot and
'cbmem' delta between 'vboot select&load kernel' and 'finished EC
verification' is reduced to ~250 ms (which includes sysjump time).
BRANCH=glados
Change-Id: I18d87e685b89decef761e51517bfcfc43dcf8ef0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326792
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Blink the LED in S3 as well as S0iX states so there is no user visible
difference in their behavior.
BUG=chrome-os-partner:49274
BRANCH=glados
TEST=Enter S0iX on chell (need SKU4) and verify LED blinks. Also verify
that the LED still blinks in S3.
Change-Id: I91b123de17787159f4e7d6aca2e86b80885b8f4e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326740
Reviewed-by: Shawn N <shawnn@chromium.org>
Setting battery charging maximum value of temperature.
If battery temperture is over than 45 degree, set charge current to
0 mA, and charge state to idle. Then LED will turn to white in idle
state.
BUG=chrome-os-partner:49695
BRANCH=glados
TEST=check the battery will not charge when battery temperture is
over than 45 degree, and LED turn to white. Then temperture is less
than 45 degree, the battery will charge and LED turn to amber.
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/323982
Reviewed-by: Shawn N <shawnn@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 4994d85d3b6c589e3ac297697aeb36456f2401a6)
Change-Id: Ic7d3fe0c482fab76041c5ae3f35402e529576b1c
Reviewed-on: https://chromium-review.googlesource.com/325487
Enable the config option for S0IX power control and set the GPIO to
use power_signal_interrupt_S0.
BUG=chrome-os-partner:49274
BRANCH=glados
TEST=echo freeze > /sys/power/state
Unfortunately currently SLP_S0_L is not asserting so this is difficult
to actually test the EC behavior
Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324567
Reviewed-by: Shawn N <shawnn@chromium.org>
Shut down all PMIC-supplied power rails rather than initiating EC / PD
hibernate. This results in considerable power savings.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual on chell. Run "hibernate" on EC console, verify that 3.3V EC DSW
rail goes to 0V, and the EC powers up on zinger insert, lid open or power
button press.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7bf0c494ea240183240f5a6abc3d611df8efb45a
Reviewed-on: https://chromium-review.googlesource.com/324087
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Enable CONFIG_BOARD_HAS_RTC_RESET and add a board_rtc_reset() function
to assert RTCRST to the PCH that will be called if the board fails to
sequence out of the S5 state.
This does not do anything on EVT devices but will be present in DVT.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell
Change-Id: If0be091349a7ef7e8e1335ade029570c5f97a30e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322725
Reviewed-by: Shawn N <shawnn@chromium.org>
The GPIOs were set incorrectly in EVT so invert them in the EC
so we can keep an incrementing board version.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=test that 'version' reports 1 for EVT board instead of 4
Change-Id: I520c3e09c7c3f0797b46807932f859aa490ac4c7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321929
Reviewed-by: Shawn N <shawnn@chromium.org>
Pull floating pins high, don't duplicate external pull ups, and make a
few other minor changes.
BUG=chrome-os-partner:48109
TEST=Verify chell continues to boot and S5 power is reduced to
~5.5 mW.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c
Reviewed-on: https://chromium-review.googlesource.com/319165
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If deep sleep S5 is supported RSMRST to the PCH should not be high
when the PCH is in S5 unless the board is sequencing out of deep sleep
and S5 state. Therefore, ensure RSMRST is low when the EC goes into
hibernate. This assumes deep sleep S5 is employed. A more appropriate
fix is to honor RMSRST state prior to going into hibernate state.
Without this change the behavior on certain platforms do not sequence
out of S5 when coming out of hibernate.
BUG=chrome-os-partner:48133
BRANCH=none
TEST=tested on a failing EVT chell board at the factory
Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If pulled up the backlight will be at 100% brightness instead of off.
BUG=chrome-os-partner:48130
BRANCH=none
TEST=hibernate on chell, see keyboard backlight stay off
Change-Id: I30cd289b9492356407aa54e6a84b04add647bd9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314936
Reviewed-by: Shawn N <shawnn@chromium.org>
Send power change event to AP whenever input power is changed,
ensure that AP gets the latest power charging info.
BUG=chrome-os-partner:47677
BRANCH=none
TEST=tested on Oak by plug/unplug AC adapter to type-C ports and
verifying the UI battery icon shows the correct status instantly.
Change-Id: I7465afcd8bc9b1c56ecf70fc74446866a8ab1b9a
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/313926
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Apply the recommended USB EQ settings for Tx and Rx channel
loss compensation to the PS8740 USB mux chip. This is called
after the driver is initialized and sets up the chip for the
first time.
BUG=chrome-os-partner:47074
BRANCH=none
TEST=build and boot on chell, read back registers to verify
> i2cxfer r 1 0x34 0x32
0x60 [96]
> i2cxfer r 1 0x34 0x3b
0x60 [96]
> i2cxfer r 1 0x20 0x32
0x60 [96]
> i2cxfer r 1 0x20 0x3b
0x60 [96]
Change-Id: I95334be9eed2858864787500a7483fa043947148
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313748
Reviewed-by: Shawn N <shawnn@chromium.org>
- Disable SLP_S0 as interrupt source for proto boards
- Remove pull-up on PLATFORM_EC_PROCHOT for EVT boards
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell proto
Change-Id: I3196e9fe1c921d66fd841c6ca1c3d8df131db9eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313663
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PCH_RTCRST signal is active high controlling the gate of a FET.
Therefore, it's default state should be low.
BUG=chrome-os-partner:47505
BRANCH=None
TEST=Built. The FET is unstuffed on both boards currently.
Change-Id: Ia0e07e67e6ea4eecf151ac8890ad98c8a337c01e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/312061
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable the option to reset the EC when the PD panics.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=verify that if PD is in RW and reboots then the EC
will panic and print "PD crash".
Change-Id: I69ab08914aef08b5ef0eaa447c142444113c526c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311308
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Change ADC channels on mec1322 boards to use scaling based on ADC
reference voltage of 3.0V instead of 3.3V. Also, setup the scaling
for AMON_BMON which reads the adapter input current or battery
current in mA.
BUG=none
BRANCH=none
TEST=tested on glados. use adc console command and verify it
roughly matches twinkie voltage and current.
Change-Id: Id6ed72012ebb1c23cf98a14ee6c156ec0f5fb586
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311302
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a new configuration struct tcpc_config_t that initially defines the
i2c host port and i2c slave address of all TCPCs present on the board.
This will allow us to create boards with multiple TCPCs on different i2c
ports, with arbitrary i2c slave addresses.
BUG=chromium:551078
TEST=Manual on glados. Verify PD communication / charging is still
functional on both PD ports.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9b2bde85d7f1642e8727c052e064371be7967619
Reviewed-on: https://chromium-review.googlesource.com/311000
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Under NVDC, BGATE natively has a body diode. Hence there's a discharging
path if VSYS is lower than VBAT. This change keeps VSYS voltage when
turning off charging.
BRANCH=none
BUG=chrome-os-partner:46698
TEST=manual
make buildall -j
load on boards with isl9237 charger.
charge the battery to full, and check charging voltage and current.
Change-Id: I8a6046444dd40a3b57f034be124b9e8fe281de40
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309289
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Some chips previously defined CONFIG_I2C and others didn't. Standardize
the usage by removing CONFIG_I2C from all config_chip files and force it
to be defined at the board level. Also, make boards define
CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces
they will use - this will assist with some later cleanup.
BUG=chromium:550206
TEST=`make buildall -j`
BRANCH=None
Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/310070
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Enable USB PD logging.
BUG=chrome-os-partner:45933
BRANCH=none
TEST=make -j buildall
make -j BOARD=glados tests
Load on glados and test that PDLOG events show up in dmesg
Change-Id: I61dbc5019ea3228542c2c244228bbb483cf51ead
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309881
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Chell was still set to use W25Q64 instead of the W25X40 that is
actually on the board.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=successfully run "flash_ec --board=chell"
Change-Id: If21e5f9a00600c97d81d2bb2a8700801ae5c2fd6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308727
Reviewed-by: Shawn N <shawnn@chromium.org>
Add VCONN swap ability and accept VCONN_SWAP requests as long
as we have the ability to provide VCONN.
BUG=none
BRANCH=none
TEST=test on glados. ask for vconn swap and make sure vconn swap
is successful.
Change-Id: I7340e6253dcde4cdbe333a9622d7826e7ccbe6b4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308238
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change battery and variable sink capabilities for all boards
to account for +/-5% voltage inaccuracy.
BUG=none
BRANCH=none
TEST=test glados with third party variable power supply and make
sure it see's our sink capabilities as 4.75V-21V.
Change-Id: I2481ccbe6c47bfed1a6b8b237329e70bd0f8e4ac
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/308237
Reviewed-by: Todd Broch <tbroch@chromium.org>
The port 80 task just polls every 1ms until disabled when the system
goes into suspend. Therefore, this commit configures a 1ms timer
interrupt that will be used for the port 80 writes instead of using an
entire task. This saves task stack space as well as context switches.
BUG=chrome-os-partner:46062
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Flash GLaDOS and verify using the `port80' console comamnd that
there are bytes in the port80 history.
TEST=make -j buildall tests
Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/305591
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The stm32 (i2c slave) datasheet provides a 500 KHz timing configuration
for Fm+ when using an 8 MHz i2c clock.
BUG=chrome-os-partner:46188
BRANCH=None
TEST=Verify no i2c errors are seen on EC-->PD I2C bus.
Change-Id: I15d51a77d4739a769fdfa15bc3c1dae82f046d42
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/306183
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
On Chell, we cannot fit all of the data in data RAM, therefore we adjust
this boundary slightly.
This should not be moved further as this represents when we are truly
out of space.
128k image:
-3k loader
-1k for shmem/panic info
-24k RAM for RO/RW
-100k for RO/RW .text and .rodata
BUG=chrome-os-partner:46058
BUG=chrome-os-partner:46063
BUG=chrome-os-partner:45690
BRANCH=None
TEST=make -j buildall tests
Change-Id: I6fbb0fd53ecb493a1821e6499276a09e93b653b9
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/305793
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
