The thermal engine monitors the temperature readings from all sensors.
For each sensor, five threshold temperatures can be set:
1. Low fan speed.
2. High fan speed.
3. SMI warning.
4. Shutdown CPU.
5. Shutdown everything we can.
Each of these thresholds can be set to either a fixed value or disabled.
Currently the real implementation of SMI warning and shutting down is
left as TODO, as indicated in the comment.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manually change threshold value to test all actions can be triggered.
Change-Id: If168dcff78ef2d7a3203cb227e1739a08eca961e
Add a task to update fan speed in LPC mapped memory once per second.
Also added read_mapped_mem16 and read_mapped_mem32.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8183
TEST="ectool pwmgetfanrpm" shows same result as "faninfo" from ec
console.
Change-Id: Ibc536acd39f836ffcad0bfa7c9c14e730220bd49
On bds, always send the keyboard scan code for the power button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I56ad8c9dd67edfd54190d64f16742896a86b9ac1
The PMIC_ACOK signal is active-low.
Let's drive it correctly.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On ADV board, check that a short key press on the power button is
now able to start the board
Change-Id: Iea71939aeb532618019a9e7774721703c632976f
Set the keyboard GPIO interrupts and task for the Daisy and ADV boards.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy
run EC firmware on ADV board.
Change-Id: I01c7f0112b7ab3382e04ad032a86fb0f3878b02b
A temperature polling task is added to achieve temporal correction and
also reduce the latency of reading temperature.
Factor out sensor specific part to keep code clean.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7801
TEST=On link, 'temps' shows all temperature readings.
Cover each sensor with hand and see object temperature rise.
Compilation succeeded on bds/adv/daisy/discovery.
Change-Id: I3c44c8b2e3ab2aa9ce640d3fc25e7fba56534b86
This loosely ports the LM4 keyboard_scan code to STM32
Notable differences:
- Keyboard GPIO layout is spread across multiple ports and is not
contiguous in many places. Because of this, bitmasks are mostly
generated on-the-fly instead of hard coded (IO is kept to a minimum)
- Longer timeout when scanning columns (100us versus 20us)
Also, some functions are stubbed out currently since they rely on
other bits being implemented:
- keyboard_state_changed()
- keyboard_has_char()
- keyboard_put_char()
BUG=none
TEST=Tested on STM32L-Discovery (monitoring keystrokes via UART)
Change-Id: I84985879589e70688b2b29b288ab17037f7668b2
Compared to Daisy, it has the EC console on USART2 (pins PA2 and PA3)
and regulator enable GPIOS EN_PP1350 and EN_PP5000 are on PA9/PA10.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy && make BOARD=discovery
Change-Id: I545f7c9b05480e58db913ea562c77a1a1cd2b11c
Avoid duplicating in each board file, the stub functions replacing not
implemented drivers on the STM32L platform.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery
Change-Id: I25cd949c31e53a90c39f623617c7d52517a3d205
Allow to set easily the SoC pins to one of their native functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, check the muxing of the USART pins is still
working and we get traces.
Change-Id: I6e83d2eea8986d814720ad4b2fef588908b99079
This should be enough to switch on the board from either the power
button or the EC console.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run Daisy firmware on Discovery board with logic analyzer attached
to GPIO pins. With an added task to simulate PMIC startup and AP
startup, check the timing chart looks good.
Change-Id: I5dfeab05d0481d121ddacb36b69a542cc1bd428c
This CL attempts to abstract underlying bus from i8042 code. Nearly
all i8042 logic is isolated already. This patch is intended to allow
us to use i8042 logic for processing keys and commands on boards which
do not necessarily use LPC as the host <--> KBC bus interface.
This CL does the following:
- Define KBC bus <--> host (kbc_host_bus) on a per-board basis in
board.c.
- Add generic wrappers in place of lpc_keyboard_* in i8042 code.
- Define the behavior of generic wrappers in EC-specific keyboard
sources. If board.c specifies LPC, then send via LPC.
TODO: This needs to be tested on real hardware...
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Locally compiled for Link, BDS and Discovery.
Change-Id: I9cabd514bd44fd6b508c26994eccc3011eedbc0f
The order of the GPIO in the header was not matching the signal list.
EC_INT is an output to trigger an interrupt on the application
processor.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy
Change-Id: Ib0eb675ad7d7e9e105b1d486c181a6df9bd5ad9b
When we are not running the ROM monitor first, we must set the pins used
for USART1 (PA9/PA10) as alternate function.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=Run firmware on the discovery board not from the monitor and see
the traces.
Change-Id: I32be3d5a88a3e71828d081d74503722331a649b8
Necessary files to build it and GPIO definitions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery && make BOARD=link
Change-Id: I22ad8d2d859f9c884bf2e3f92db02d992ad669a6
BUG=chrome-os-partner:7839
TEST=none, work in progress
Change-Id: I20acde8db7f250227adcd4b9dc59328362e68720
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Remove id field from temp_sensor_t struct, since it's only used by the
console command (which already knows the id, because it's looping over
it).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='temps'
Change-Id: I0970850073d644509cd5501d7ac4421c7373143b
This change adds a common part of smart battery driver. Following
features are not implemented, or in chip specific driver:
Battery access control, authentication, factory mode
Manufacturer access/data commands
Block read/write, device name, flash data
Chip specific features, per cell info/temp/capacity
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7856
TEST=console command check battery staus
[unplug power]
> battery
[check voltage,current,capacity,time to empty]
[plug power]
> charger voltage 8400
> charger current 4250
> battery
[check current,time to full]
> charger input 4032
> battery
[check current,time to full]
[wait 130 seconds, charger watch dog timeout]
> battery
[check current]
Change-Id: Ifac17a0892f52e8f37eebc14b00e71f18360776c
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7493
TEST='powerbtn' to boot main processor, then 'temps' and 'pecitemp'
Change-Id: Id57526ebb37c8aecb05ecebccc2824f462b9de1a
The Daisy board will have the EC UART on the debug connector wired to
USART1 (PA9/PA10 pins)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=Run Discovery board with mini-servo attached to PA9/PA10 and see
the traces.
Change-Id: I97c59ba388fddb150ff6c76ec3317deedb567546
Implement TMP006 object temperature calculation. Also add a console
command to calculate temperature with manually entered data.
BUG=chrome-os-partner:7801
TEST=In console, "tempremote 29715 -105000 6390" gives 285.00K.
Change-Id: I0f9193fb970fdc36566399e7083e73ab58965a85
Battery charging state machine contains many file changes.
This is the 1st part of the break down. Refactor original
test code into board dummy driver. Normalize charger API.
And import link's charger IC driver.
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7855
TEST=build without warning and error
BOARD=bds make
BOARD=link make
BOARD=discovery make
Change-Id: I34b6e9862a45331378916bc77653d4adb22ca548
Current makefile takes CONFIG_* flags from $(CHIP)/config.h . This
CL adds $(BOARD)/board.h and a sample charger config flag.
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7917
TEST=build bds,link board and check warning and error messages.
Change-Id: I1f13d24da6b18c014f40f941ef7245487e5ccc81
Refactor board/chip-specific code into corresponding directories.
Add support of the four I2C temp sensor in Link.
Use table lookup to handle different types of temperature sensors.
BUG=chrome-os-partner:7527
TEST=Correctly read EC internal temperature on bds.
Compile for link succeeded.
Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
No interrupt support yet.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery EC console, using "gpioget" and "gpioset" commands
check we can switch the LED and read the button state.
Change-Id: I01294643d3df070a535dab5a6be02c296487fca5
Use the Independant WatchDog.
The Window WatchDog would provide a nice early warning interrupt before
actually rebooting but the max period (128 ms) is probably too short for
our purpose.
The full GPIO support and the reboot cause detection will be implemented
in later steps.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, do blocking waits of 500ms and 1500ms, and
check the latter reboots the platform and the former does not.
Change-Id: I26e4d8b26b733269b7811cc3b3a09daf98ea364a
The ADC input pin was always configured as BDS. Modified it to configure
the correct pin.
BUG=none
TEST=On Link, "rw 0x4002451C" show 0xff instead of 0xf7.
Change-Id: I1efd5cd59ad65f55cd673529afa6153add63ecac
Refactor ADC code and move board/chip-specific part to corresponding
directories.
Implement function and console command to read Link charger current.
BUG=chrome-os-partner:7527
TEST=Read EC temperature and POT input on BDS.
Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
simple UART driver to get the serial console on the USART3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on Discovery board and check we get the first message on the
UART and the console is echoing the characters.
Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
Run from internal clock at 16Mhz, but enable PLL to get a better
precision.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on discovery board and check software is still alive after
clock initialization.
Change-Id: I8425482825015adf96c30e67a9320d0df2f4f2b7
All hardware drivers code is stubbed excepted a few configuration
settings.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=discovery
Change-Id: Ic9e88a0f51ab626679c8aeb6192272e66a3f79b8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=push and release power button; should see debug messages
Change-Id: I4a08b56247baa85555514623db7a04ab4638ca0e
This fixes linker errors when the X86_POWER and/or POWERBTN tasks are disabled.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=remove X86POWER and POWERBTN tasks from ec.tasklist and make
Change-Id: I8a95020925e32ac4f80b9363f5aa6ab0a2d9ccd1
You can now enable/disable tasks more easily.
To conditionally compile a C file depending on the task FOO activation,
just write something like that in the build.mk file :
common-$(CONFIG_TASK_FOO)+=foo_source.o
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make all BOARD=link && make qemu-tests
Change-Id: I760fb248e1599d13190ccd937a68ef47da17b510
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7697
TEST=if it runs, it works
Change-Id: I36ab37a8cf1c3e4bf41bfb38e622e766cee8a4c4
When code is compiled for RAM (by re-enabling the flag in board.mk),
use the following openocd commands to load it:
reset halt
load_image ../../../build/link/ec.RO.flat 0x20000000 bin
reg 15 0x20000400
resume
Note that you'll also usually need to disable a bunch of modules to make
the code small enough to fit in RAM.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7681
TEST=if it runs, it works
Change-Id: I2b3cc69b361ad73706af3ff6de1ce952e8d5a0a9
Implement TPS2543 USB charging control.
It contains routine for setting each USB port as dedicated charging port
or standard downstream port. To allow us controlling the current
distributed to each port, we can select whether to allow 500mA or 1500mA
for each port.
BUG=chrome-os-partner:7476
TEST=Added USB port definition for BDS and tested GPIO output voltage
level is correct for all modes.
Change-Id: I19bc4b30d333aa802f868ebfc3a398b30e99ba0f
