State machines implemented using deferred functions need to be able to
kick off deferred function from a HOOK_INIT handler. But tasks aren't
running in HOOK_INIT, so task_wake() fails.
Instead, hook_call_deferred() should check to see if the hook task has
had a chance to run yet. If it hasn't, then there's no need to wake
it; it'll get run eventually anyway.
BUG=chrome-os-partner:24892
BRANCH=rambi
TEST=Add a call to hook_call_deferred() in a HOOK_INIT handler. It shouldn't
crash, and the deferred function should be called.
Change-Id: I5c8077b636ae030a668a211fd8238549b6bcfa54
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181953
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Unexpected EOF usually means error in the test code or assertion
failure. In this case, let's treat it as test failure.
BUG=chrome-os-partner:19235
TEST=Check assertion failure fails the test.
BRANCH=None
Change-Id: I9270d223d7252f611673a2c55af0c2d68b6116c4
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181747
The variable 'interval' is declared as unsigned integer, and this
sometimes causes an integer underflow when substracting it by SECOND,
and in turns leads to false test failure. Changing it to signed integer.
BUG=chrome-os-partner:19236
TEST=Repeatedly run hooks test
BRANCH=None
Change-Id: Ic6d8001f90fb8756b6bdadf811a668c02fbccb34
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181882
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This prevents an interrupt from being triggered when we happen to be
enabling/disabling global interrupt.
BUG=chrome-os-partner:19235
TEST=Repeatedly run interrupt test
BRANCH=None
Change-Id: I0163aff801ddbcee4aedba7a78966d97336c79ca
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181920
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Emulator test failures are sometimes hard to debug, especially when the
test is stuck somewhere and times out. Let's have the emulator dump
stack trace when an assertion fails or a test times out.
The produced stack trace is in this format:
#0 build/host/kb_8042/kb_8042.exe() [0x412421]
/home/victoryang/trunk/src/platform/ec/test/kb_8042.c:104
#1 build/host/kb_8042/kb_8042.exe() [0x4124a9]
/home/victoryang/trunk/src/platform/ec/test/kb_8042.c:129
#2 build/host/kb_8042/kb_8042.exe(run_test+0x3a) [0x412e2c]
/home/victoryang/trunk/src/platform/ec/test/kb_8042.c:262
#3 build/host/kb_8042/kb_8042.exe(_run_test+0x11) [0x4061de]
/home/victoryang/trunk/src/platform/ec/core/host/task.c:90
#4 build/host/kb_8042/kb_8042.exe(_task_start_impl+0x79) [0x406b72]
/home/victoryang/trunk/src/platform/ec/core/host/task.c:408
#5 /lib64/libpthread.so.0(+0x70b1) [0x7f6dc2fa10b1]
??:0
#6 /lib64/libc.so.6(clone+0x6d) [0x7f6dc2cd8efd]
??:0
The file name and line number in the trace is generated by addr2line.
BUG=chrome-os-partner:19235 chromium:331548
TEST=Put in a infinite loop in a test, and see stack trace when it times
out.
TEST=Add a failing assertion, and see stack trace when it fails.
BRANCH=None
Change-Id: I4494ffd1ebc98081ce40e860a146202084aa2a1e
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181730
On the IT8380, we should be able to map 16kB of SRAM to use as data
memory (aka DLM), but sometimes the 2 top 4k pages seem to be
mapped differently (ie not to SRAM, they do not retain writes ...).
As we have no documentation on that topic, for now use 8kB of DLM for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:23575
TEST=build and run IT8380 dev board.
Change-Id: I4ed452f27e9c457e7ac717b82580781ca506b0d8
Reviewed-on: https://chromium-review.googlesource.com/179322
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
When jumping between image copies, we need to preserve the test fail
count. Otherwise tests failed before the jump would be silently ignored.
BUG=chrome-os-partner:19235
TEST=Fail a test case before sysjump and check the whole test fails.
BRANCH=None
Change-Id: Iebde40141f62ac067ddabf629add46e5d752d674
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181746
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The mock system_usable_ram_end() always returns the same address.
However, this causes the second jump tag to overwrite the first one.
Also, now that the jump data is properly placed, we can actually remove
the mock implementation.
BUG=chrome-os-partner:19235
TEST=Add two jump tag and check the first one is not overwritten.
BRANCH=None
Change-Id: If868895a7c028dd25399adb69e9708de45c84f10
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181745
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The mock power button GPIO is initially low, so we need to set it high
before testing it. Also, wait for all tasks to start before starting the
test to prevent race condition.
BUG=chrome-os-partner:19236
TEST=Pass the test
BRANCH=None
Change-Id: I813588a9c721815c1213882f7a9458daea4d78eb
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181744
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Initial support for the ITE IT8380 chip with the following peripherals :
- 8250-like UART module.
- HW timer (with a 128-us tick period).
- GPIO with pins initialization and edge interrupt support.
other functions are stubbed.
- Clock : basic fixed frequency setup only.
It also add the dev board configuration as a test vehicle.
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:23575
TEST=make BOARD=it8380dev
on IT8380 dev board, use the EC serial console, use gettime from
console.
Change-Id: Id4bf37d1beb21d1a4bee404c9a0bc500025fe787
Reviewed-on: https://chromium-review.googlesource.com/175481
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
It was udelay, which is busy-loop and other tasks have no chance to run.
usleep() could yield the CPU resource out.
BUG=None
BRANCH=nyan
TEST=other tasks get chance to run.
- Before:
[0.010242 not sysjump; forcing AP shutdown]
[0.060471 EC triggered warm reboot]
- After:
[0.010103 not sysjump; forcing AP shutdown]
[0.022985 event set 0x00000080]
[0.041828 Charge state init -> idle0 after 0.010393 sec]
[0.043327 Battery 98% / 1092h:15]
[0.060394 EC triggered warm reboot]
Change-Id: Id41a0b4fda5ac78b1b7f3e3f316b9721fcc3dd34
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181763
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Implement LED color policy (crosbug.com/p/23957)
Update battery vendor information (crosbug.com/p/24684)
BUG=chrome-os-partner:24885
BRANCH=rambi
TEST=manual
system on, lidclose -> power LED off
system on, lidopen -> power LED on
system suspended -> power LED blinks green every 2 sec
system suspended, lid closed -> power LED off
system off -> power LED off
plug AC in, battfake 95 -> charging LED green
plug AC in, battfake 94 -> charging LED orange
unplug AC, battfake 10 -> charging LED off
unplug AC, battfake 9 -> charging LED blinks orange
battcutoff -> after a few sec, system powered down
plug back in AC -> system comes back on
charger -> I_in < 1700
Change-Id: I89161e2c024d85197b8612a40a61dd50c106549e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181755
The SERIRQ signal will now be high-Z on the EC, which removes a
leakage path. This requires the BIOS to use PM3 for its keyboard IRQ.
BUG=chrome-os-partner:24424
BRANCH=rambi
TEST=boot system; keyboard still works
Change-Id: I0acf425125ced11a9ef6da58ee49979b83c92d5c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181718
After this change, only Rambi 2.0 boards will boot properly.
This cleanup is necessary before supporting other Baytrail systems.
BUG=chrome-os-partner:24414
BRANCH=rambi
TEST=as soon as I get a 2.0 board
Change-Id: Ic9e3afcee9dae5c0b7f31a7aa4500b2572ba92c6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181754
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Those are actually charge state, not power state. Rename the misleading
names.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy,spring,pit,snow
TEST=build only because no name conflicts.
make clean BOARD=link && make -j32 BOARD=link && \
make clean BOARD=falco && make -j 32 BOARD=falco && \
make clean BOARD=samus && make -j 32 BOARD=samus && \
make clean BOARD=rambi && make -j 32 BOARD=rambi && \
make clean BOARD=peppy && make -j 32 BOARD=peppy && \
make clean BOARD=snow && make -j 32 BOARD=snow && \
make clean BOARD=spring && make -j 32 BOARD=spring && \
make clean BOARD=pit && make -j 32 BOARD=pit && \
make clean BOARD=nyan && make -j 32 BOARD=nyan && \
make runtests -j 32 && make tests -j 32 BOARD=link && \
make tests -j 32 BOARD=falco && make tests -j 32 BOARD=samus && \
make tests -j 32 BOARD=rambi && make tests -j 32 BOARD=peppy && \
make tests -j 32 BOARD=snow && make tests -j 32 BOARD=spring && \
make tests -j 32 BOARD=pit && make tests -j 32 BOARD=nyan
Change-Id: Ie15052d5a7dbd97d519303d37260945346a27779
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181505
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Renaming file names is the first step. Please see issue tracker
for more details.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy
TEST=build all x86 boards.
make clean BOARD=link && make -j32 BOARD=link && \
make clean BOARD=falco && make -j32 BOARD=falco && \
make clean BOARD=samus && make -j32 BOARD=samus && \
make clean BOARD=rambi && make -j32 BOARD=rambi && \
make clean BOARD=peppy && make -j32 BOARD=peppy
Change-Id: I3a296a0c14f6bebefa858438b1320061ac71dd38
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181400
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It will be used by all variants of Rambi, so #ifdef BOARD_RAMBI is too
restrictive.
BUG=chrome-os-partner:24864
BRANCH=rambi
TEST=boot rambi 1.5 board; plug in USB mouse
Change-Id: I0ff02077388a6c6621c5746a693dde894cf8ad77
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181682
Reviewed-by: Alec Berg <alecaberg@chromium.org>
We changed the behavior of indata.size==0 case in cros_ec kernel driver.
This breaks the nyan battery driver. Change the ectool as well.
BUG=chrome-os-partner:24851
BRANCH=nyan
TEST=verified on nyan rev B
% ectool battery
Battery info:
OEM name: SANYO
Model number: AP13J3K
Chemistry : LION
Serial number: 174E
Design capacity: 4030 mAh
Last full charge: 4030 mAh
Design output voltage 11250 mV
Cycle count 0
Present voltage 12934 mV
Present current 0 mA
Remaining capacity 3966 mAh
Flags 0x03 AC_PRESENT BATT_PRESENT
Change-Id: Id63d933802ed85d7f5d8f1c53e6389b083f41a8a
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On early snow boards, WP GPIO is not wired to the EC. Now that we have
properly fixed hardware, we should drop workaround for those boards.
BUG=chrome-os-partner:23762
TEST=Build all boards
BRANCH=None
Change-Id: I5dcfaf5497fc36d6b8d7bc5d8975aa18b2d36a1d
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181090
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Currently emulator UART input/output are processed in various context,
including UART thread, individual tasks, and tests. By moving the
processing to interrupt context, the way it works resemble real chips
more. Also, this provides a cleaner cut between emulated UART device and
UART processing code.
BUG=chrome-os-partner:23804
TEST=make buildall
BRANCH=None
Change-Id: I58127e66f4058a68d37be9029e9ddbbd798381c6
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181590
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This provides us a way to inject interrupts during a test. If a test has
interrupt_generator() defined, it will run in a separate thread. The
generator can then trigger interrupts when it decides to. The current
running task is suspended while emulator is executing ISR.
Also fixes a bug that tasks run without scheduler notifying them during
emulator start-up.
BUG=chrome-os-partner:19235
TEST=Repeatedly run all tests.
BRANCH=None
Change-Id: I0f921c47c0f848a9626da6272d9040e2b7c5ac86
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/55671
KBD_IRQ_NEW_L (added for Rambi 2.0) has a pull-up resistor and should be
open drain.
TEST=None
BUG=chrome-os-partner:24760
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibf1beff3306c074f9f135b1bee82e299edf2380b
Reviewed-on: https://chromium-review.googlesource.com/181227
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For AP hang detection, the warm reset must be implemented. Since
the cold reset is easy, implement it at the same time.
BUG=chrome-os-partner:23822, chrome-os-partner:24789, chrome-os-partner:24558
BRANCH=nyan
TEST=on nyan rev 3.12
power on/off --> work as usual
power on, then apreset cold --> system is cold reset (off, then on)
power off, then apreset cold --> nothing happens. this is fine.
power on, then apreset warm --> system is warm reset (power trail is kept).
power off, then apreset warm --> nothing happens. this is fine.
power on --> system is back to normal again.
Change-Id: I010793b7a2d309e5d606fbc5877e9e3b07c8c5f3
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181164
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Old code reset some GPIO configurations with af->flags = 0 while
gpio_config_module(). This is bad because it could lead unexpected
behavior on the bus.
New code accepts GPIO_DEFAULT flag so that it doesn't touch the
GPIO setting while configuring alternate functions. This should not
effect other boards unless the GPIO_DEFAULT is set on that board.
BUG=chrome-os-partner:24607
BRANCH=nyan
TEST=run on nyan rev 3.12. No "SPI rx bad data" at boot. UART and i2c good.
Change-Id: Id451cfae21e1d764452429dc5adfe1317ff5b140
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181135
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Follow up Randall's CL 616e709. Note that the nyan warm reset is in
another CL.
BRANCH=nyan
BUG=chrome-os-partner:24558
TEST=See test procedure and results on comment #7 of issue 24558.
Note that the suspend tests cannot be done because my nyan cannot suspend.
Change-Id: I77c59cab177bc2c6fdf9bb8828937fc7b84e6d76
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181177
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This includes:
- Reference to the boot ROM document
- Update flags usage from the document
- Command line argument support
BUG=chrome-os-partner:24107, chrome-os-partner:24188
TEST=Pack and boot
BRANCH=None
Change-Id: I6f79ca94fbc10448e3a1c884a2d52fdf4abf266d
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180180
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Adding two signing keys:
- A dev key used to sign header. We have confirmation from Microchip
that we can check in this key.
- A key to sign payload. This can actually be an arbitrary key as long
as the header and the payload are in sync. Adding a key here just
for convenience.
BUG=chrome-os-partner:24107
TEST=None
BRANCH=None
Change-Id: I5d7418a926047887c01cd0a334a041b18082f66e
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180835
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
By merging make_all.sh to Makefile, parallel make can be made faster.
Previously, if one does 'util/make_all.sh -j32', most of the time is
spent on waiting for linking. Now that we invoke sub-make, linking an
executable doesn't block the next board.
With '-j32', the new 'make buildall' takes about 7 seconds, while the
original 'util/make_all.sh' takes about 27 seconds.
BUG=None
TEST=make buildall -j32
BRANCH=None
Change-Id: I7c2f0d1e928a9b60a8a9070bdcb71b00a3d534cd
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181091
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The igloo board has a different product ID than bds board. Add the new
product ID to ec_uartd.
BUG=chrome-os-partner:24713
TEST=Run ec_uartd with igloo board
BRANCH=None
Change-Id: Idcbb08072661e12ed744a60fb04a55d4f58cf89b
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181082
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We have three copies of the same pseudo random number generator in our
test codes. Let's consolidate them into a single copy in test_util.
BUG=chrome-os-partner:19235
TEST=Pass all tests
BRANCH=None
Change-Id: I7ea0b3476f3cfe6944855f19861e3c86af35807e
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181085
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ADC driver for MEC1322 with ADC interrupt support.
BUG=chrome-os-partner:24107
TEST=Read single channel
TEST=Read all channels
BRANCH=None
Change-Id: I89d196c7fd78e736575e2c368b65cfb1ec651004
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180832
We have three duplicated ADC read console command, and we are about to
have the fourth. Let's consolidate them to a single implementation in
common/.
Note that we have to add a simple implementation of
adc_read_all_channels() for LM4.
BUG=chrome-os-partner:18343
TEST=Build all boards
TEST=Read single channel
TEST=Read all channels
BRANCH=None
Change-Id: I079c0b33ab6b81a188f309cf99875eb02e9d78a4
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180831
The first time the PMIC sees power (AC or battery) it needs 200ms
(+/-12% oscillator tolerance) for the RTC startup. In addition
there is a startup time of approx. 0.5msec until V2_5 regulator
starts up.
BUG=None
BRANCH=nyan
TEST=verified on rev 3.12 with AC/battery replug * 10.
Power button on/off and 'power on/off' are not effected.
Change-Id: I706829017a53c549601a925cb18d33b21c50eb76
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180677
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This lowers, the WARN, HIGH, and HALT temp thresholds
for x86 boards to below their CONFIG_PECI_TJMAX value.
Also lowers the FAN_MIN and FAN_MAX temps by 5 degrees on
Haswell boards to compensate for lowering TJ_MAX by 5 degrees
in an earlier patch.
BUG=chrome-os-partner:24455
BRANCH=none
TEST=Manual. Run boards without a fan and without any host-side
throttling. Verify that board either reaches a steady state temp
due to throttling or hits SHUTDOWN and turns off before EC reset
is triggered.
Change-Id: I499baa0b4100201525e69752af3465feb592262c
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179886
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
According to the nVidia power engineer, we shall wait for 40ms to see
XPSHOLD asserted after PMIC_PWRON_L is asserted.
Also change the code since it was obscured. Comments was out-of-sync too.
BUG=None
BRANCH=None
TEST=Verified on rev 3.12.
Change-Id: If479d8398f4008f0b029d450b3d28ac98cdf969f
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
AP throttling in the thermal task ends up calling a pretty deep nested
set of calls, and in the worst case can overflow the stack. Bump up
the stack size for the hook task on x86 platforms to compensate.
BUG=chrome-os-partner:24536
BRANCH=peppy/falco
TEST=taskinfo shows hook task increased from 512 to 640 bytes stack
shmem shows at least 4000 bytes free
Change-Id: I63da7c47b993c935d895f91d787844655071da0d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180684
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
So that Tegra wants to drive the PMIC_WARM_RESET_L low it will not be
fighting the EC.
BUG=None
BRANCH=None
TEST=Verified on the board rev 3.12
Change-Id: I5980a3ba096c152a4ccc28ad64e675c53b7cb337
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This make minor syntactic changes and renames some camel-cased symbols
to keep checkpatch from complaining. The goal is to reduce the
temptation to use 'repo upload --no-verify'.
This is a big furball of find/replace, but no functional changes.
BUG=chromium:322144
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180495
We've had uppercase macros (BOARD_FOO) for a week for
PROJECT_
BOARD_
CORE_
CHIP_
CHIP_FAMILY_
CHIP_VARIANT_
and I've just made a pass to fix the last leftover mixed-case usage
from changes that were in flight when I made the initial cleanup. It
is now time to remove the old mixed-case macros (BOARD_foo).
BUG=chromium:322144
BRANCH=none
TEST=Build all boards. Diff build/$(BOARD)/ec.RO.map before and after
this change. Should be no changes - indicating that the same code
was compiled before and after.
Change-Id: Ic5a1e83d31be4b8e9fdbacc3eb10176fd126d84a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180384
All macros are now uppercase.
BUG=chromium:322144
BRANCH=none
TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no
results (similarly for CHIP, CORE, TEST, CHIP_FAMILY, CHIP_VARIANT.)
Change-Id: I04850e569b3950bb88f9dff107de06dfa49b04fc
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180430
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When a GPIO signal is defined by GPIO_SIGNAL_NOT_IMPLEMENTED, it should
still be able to call various GPIO methods on that GPIO signal. Since
__builtin_clz dies when the value passed in is zero, we need to check
this before calling __builtin_clz.
BUG=chrome-os-partner:24107
TEST='sysjump RW' and the system doesn't crash
BRANCH=None
Change-Id: I5025a2f218d549316fe096c07bd3c7207fe9dbc2
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180183
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This implements i8042 keyboard interface at LPC 0x60/0x64.
BUG=chrome-os-partner:21407
TEST=Enable keyboard and keystroke from host ACPI commands. Short KSO
pins and KSI pins, and read different key codes from host.
BRANCH=None
Change-Id: Ie4e5e236bdeefd7e44974f92fcbafab5e4af2b30
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179940
The spec does not mandate any way to read back the threshold settings
themselves, but when a threshold is crossed the AP needs a way to determine
which sensor(s) are responsible. Each reading of the EC_ACPI_MEM_TEMP_ID
register clears and returns one sensor ID that has crossed one of its
thresholds (in either direction) since the last read. A value of 0xFF means
"no new thresholds have tripped". Changing or enabling the thresholds for
any sensor will clear the unread event count for that sensor.
BUG=chrome-os-partner:23970
BRANCH=none
TEST=manual
On the host, set a couple of thresholds to low values so they trip
immediately (I'm testing on Link):
# dptf() {
[ "$#" -eq "2" ] || return;
iotools io_write8 0x66 0x81
iotools io_write8 0x62 $1
iotools io_write8 0x62 $2
}
#
# dptf 5 0
# dptf 6 10
# dptf 7 3
# dptf 5 2
# dptf 6 10
# dptf 7 2
On the EC console, see that two thresholds have triggered, and that there
are two bits set in the AP seen mask:
[45.755365 DPTF sensor 0, threshold -63 C, index 1, enabled]
[45.768940 DPTF sensor 2, threshold -63 C, index 0, enabled]
[46.169490 DPTF over threshold [0][1]
[46.169820 DPTF over threshold [2][0]
> dptftemp
sensor thresh0 thresh1
0 --- 210* I2C-USB C-Die
1 --- --- I2C-USB C-Object
2 210* --- I2C-PCH D-Die
3 --- --- I2C-PCH D-Object
4 --- --- I2C-Hinge C-Die
5 --- --- I2C-Hinge C-Object
6 --- --- I2C-Charger D-Die
7 --- --- I2C-Charger D-Object
8 --- --- ECInternal
9 --- --- PECI
AP seen mask: 0x00000005
>
Read the EC_ACPI_MEM_TEMP_ID register from the host, to get the two active
sensor IDs (0 and 2), then 0xff when those are seen.
# iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62
0x00
# iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62
0x02
# iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62
0xff
# iotools io_write8 0x66 0x80; iotools io_write8 0x62 5; iotools io_read8 0x62
0xff
#
Change-Id: I8f047a517357617f18ad59d21fa13409bc81821b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180224
Reviewed-by: Randall Spangler <rspangler@chromium.org>
SOC_OVERRIDE now drives a FET, so the signal is inverted (high=active,
not low). EC must drive it push-pull because there is no
pullup/pulldown on the input to the FET.
BUG=chrome-os-partner:24118
BRANCH=none
TEST='gpioget' shows signal is 0 by default, not 1.
Change-Id: I8a86587c7fad8bf5a583cd3976bd6ed3069f2975
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180287
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Proto 2.0 makes these changes:
KBD_IRQ# moves from PM4 to PM3.
EC_PWROK moves from PH2 to PJ1.
Since PM3 and PJ1 are unused on proto 1.5, it's harmless to duplicate
the current functionality on those outputs. We can remove the old
outputs when we deprecate the 1.5 boards.
BUG=chrome-os-partner:24424
BRANCH=none
TEST=boot rambi
Change-Id: Iff77651ef575a8405878fe75f025a0507b02b771
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180081
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This renames constants used in compiler conditionals to uppercase.
BOARD_foo
CHIP_foo
CHIP_FAMILY_foo
CHIP_VARIANT_foo
CORE_foo
Mixed-case constants are still defined by the makefile, but are now no
longer used. I will make one more pass in a week or so to catch any
that are part of someone else's CL, since otherwise this change might
silently merge correctly but result in incorrect compilation. Then I
will remove defining the mixed-case constants.
BUG=chromium:322144
BRANCH=none
TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no
results (similarly for CHIP, CORE, etc.)
Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179206
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This wires 0x62/0x66 to ACPI module and also implements the host event
functions.
BUG=chrome-os-partner:24107
TEST=ACPI memory test and compliment memory test.
TEST=Set SCI mask and host event to trigger SCI. Check SCI pin pulse
low.
TEST=Query host event from ACPI.
BRANCH=None
Change-Id: Ib1f557e995a861c92a603491229ad361e17d2129
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179942
Reviewed-by: Randall Spangler <rspangler@chromium.org>
