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02ec04d215
In order to meet the panel power sequencing requirements the backlight enable needs to be delayed by 420ms. As the EC has direct control over the panel backlight, it's difficult to align with the reset of the panel signals which are controlled by an LVDS bridge. In order to not affect other boards the backlight implementation has been moved within falco's board directory. BUG=chrome-os-partner:21234 BRANCH=falco TEST=Built with a printf to verify rough timing transitions. Change-Id: I5d6cd2989f17cc5c188d307f6ceacb52341a87b4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66238 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In the most general case, the flash layout looks something like this: +---------------------+ | Reserved for EC use | +---------------------+ +---------------------+ | Vblock B | +---------------------+ | RW firmware B | +---------------------+ +---------------------+ | Vblock A | +---------------------+ | RW firmware A | +---------------------+ +---------------------+ | FMAP | +---------------------+ | Public root key | +---------------------+ | Read-only firmware | +---------------------+ BIOS firmware (and kernel) put the vblock info at the start of each image where it's easy to find. The Blizzard EC expects the firmware vector table to come first, so we have to put the vblock at the end. This means we have to know where to look for it, but that's built into the FMAP and the RO firmware anyway, so that's not an issue. The RO firmware doesn't need a vblock of course, but it does need some reserved space for vboot-related things. Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If we reserve 4K at the top of each FW image, that should give us plenty of room for vboot-related stuff.