Divya Jyothi 269c330f0e mec1322: Add SPI flash layout for lfw / ro / rw architecture
mec1322 bootloader looks for a CRC TAG at the xFF00 boundary of the
flash before it loads the ec onto SRAM for execution. Code for EC will
be packed to occupy the last 256k of Flash. That way the binay generation
is independent of the flash size. The last 20000h is RO + lfw followed by
20000h space for RW.

BUG=chromium:37510
TEST=make -j buildall
BRANCH=None

Change-Id: Ie75bd8a40826d630b3022b5b3ecb2d6ad3aa2471
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265885
Reviewed-by: Shawn N <shawnn@chromium.org>
2015-04-23 00:13:50 +00:00
2015-04-21 00:18:50 +00:00
2015-04-21 00:18:50 +00:00
2014-03-31 22:45:09 +00:00
2012-05-11 09:11:52 -07:00
2014-04-02 19:58:53 +00:00
2014-05-15 05:20:14 +00:00

For an overview of the Embedded Controller firmware, refer to

http://www.chromium.org/chromium-os/2014-firmware-summit
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