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mec1322: Add SPI flash layout for lfw / ro / rw architecture

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mec1322 bootloader looks for a CRC TAG at the xFF00 boundary of the
flash before it loads the ec onto SRAM for execution. Code for EC will
be packed to occupy the last 256k of Flash. That way the binay generation
is independent of the flash size. The last 20000h is RO + lfw followed by
20000h space for RW.

BUG=chromium:37510
TEST=make -j buildall
BRANCH=None

Change-Id: Ie75bd8a40826d630b3022b5b3ecb2d6ad3aa2471
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265885
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Divya Jyothi
2015-04-16 15:20:34 -07:00
committed by ChromeOS Commit Bot
parent 54e523a3ff
commit 269c330f0e
1 changed files with 24 additions and 1 deletions
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25
chip/mec1322/config_chip.h
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@@ -84,8 +84,31 @@
#define CONFIG_FW_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
/****************************************************************************/
/* SPI Flash Memory Mapping */
/*
* TODO(crosbug.com/p/37510): Implement a loader to load either RO or RW at
* Size of total image used ( 256k = lfw + RSA Keys + RO + RW images)
* located at the end of the flash.
*/
#define CONFIG_FLASH_BASE_SPI (CONFIG_SPI_FLASH_SIZE - (0x40000))
#define CONFIG_RO_WP_SPI_OFF 0x20000
#define CONFIG_RO_SPI_OFF 0x20000
#define CONFIG_RW_SPI_OFF 0
#define CONFIG_RO_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \
CONFIG_RO_SPI_OFF)
#define CONFIG_RW_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \
CONFIG_RW_SPI_OFF)
/* Memory Location shared between lfw and RO/RW image */
/*
* TODO(crosbug.com/p/37510): Alter to the right value when lfw + Ro/RW
* architecture is enabled.
*/
#define SHARED_RAM_LFW_RORW 0
/*
* TODO(crosbug.com/p/37510): Implement a lfw to load either RO or RW at
* runtime. Since this doesn't exist yet and we're running low on program
* memory, only flash + load RW for now.
*/