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To configure 1 MHz speed when the APB clock is 15 MHz, the firmware currently sets the SCLHT register to 4. However, we found out that writing 4 to this register (and to SCLLT register) is illegal and results in unexpected results. So there is a need to write 5 in that case. However, this means that the actual i2c frequency will be 750 KHz. To get a higher i2c clock frequency, there is a need to run with a higher APB clock (and a higher core clock). For example, with APB set to 20 MHz, the i2c clock frequency is 833 KHz. In this CL, the i2c freq setting for APB clock=20 MHz is also added which may be used for NPCX7 in the future. BRANCH=none BUG=chromium:714314 TEST=No build error for make buildall(except gru). Use scope to capture SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz. Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/484202 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly