Sam Hurst 90383450f6 usb: activate CRS on STM32F0 ...

Enable the Clock Recovery Subsystem to automatically adjust the internal
HSI48 clock for proper USB operation on the STM32F0.

BUG=chrome-os-partner:34160
TEST=Manual testing on STM32F072B-DISCOVERY
	Plugged in board and verified that device was detected with dmesg.
	[1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd
	[1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f
	[1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0
	[1400698.720072] usb 3-10: Product: PDeval-stm32f072
	[1400698.720075] usb 3-10: Manufacturer: Google Inc.
BRANCH=none

Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236
Reviewed-on: https://chromium-review.googlesource.com/433059
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

2017-01-26 18:43:53 -08:00

..

g

g: common: introduce generic crypto API

2017-01-25 22:12:28 -08:00

host

fix memory size calculations in host/test mode

2016-12-28 21:49:39 -08:00

ish

ISH: Added UART Rx/Tx interrupt mode

2017-01-11 14:46:29 -08:00

it83xx

it83xx: lpc: do not clear masks in S0ix -> S0 transition

2017-01-25 02:02:58 -08:00

lm4

clock: Fix clock_wait_cycles() asm

2016-11-18 20:07:08 -08:00

mec1322

intel_x86: Make common code for LPC S0 <-> S0ix transitions

2017-01-21 10:03:45 -08:00

npcx

npcx: i2c: Fixed bug ec returns error during reading last byte.

2017-01-26 01:45:44 -08:00

nrf51

cleanup: DECLARE_CONSOLE_COMMAND only needs 4 args

2016-08-24 16:30:10 +00:00

rotor

rotor: Add DMA & SPI master drivers.

2016-09-13 22:21:44 -07:00

stm32

usb: activate CRS on STM32F0

2017-01-26 18:43:53 -08:00