Shawn Nematbakhsh 813e56e10a stm32f0: i2c: Set timing register values by port clock source ...

I2C1 may be clocked by HSI or SCLK. I2C2 is always clocked by PCLK.
Therefore, apply different timing register values according to the
selected clock source for a port.

BUG=chrome-os-partner:46188
BRANCH=None
TEST=Manual on glados_pd. Verify slave i2c communication is functional.

Change-Id: Icd2306d25d5863b0fc3379e46885a227efb23cca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309781
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>

2015-10-30 14:33:29 -07:00

..

g

cr50: upgrade to the latest FPGA image 20151029_41713@78167

2015-10-30 14:33:28 -07:00

host

cleanup: Put chip-specific configs in config_chip.h

2015-09-21 10:04:35 -07:00

it83xx

it8380dev: gpio - remove comment about E4

2015-10-25 09:17:44 -07:00

lm4

cleanup: Put chip-specific configs in config_chip.h

2015-09-21 10:04:35 -07:00

mec1322

mec1322: Abort curr DMA xfer in dma_disable_all().

2015-10-19 21:26:50 -07:00

npcx

nuc: Remove unnecessary NPCX_EC_FLASH_SIZE definition in npcx.

2015-10-19 21:26:52 -07:00

nrf51

cleanup: Put chip-specific configs in config_chip.h

2015-09-21 10:04:35 -07:00

stm32

stm32f0: i2c: Set timing register values by port clock source

2015-10-30 14:33:29 -07:00