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548e4d9708
Keep the timestamp of the latest power lost. Add a handler to wake the chipset task to check if power lost stays low for a while (the time between now and the latest power lost is longer than a period). BRANCH=none BUG=b:78455067 TEST=Toggle EC GPIO SYS_RST_L for a low pulse to execute PMIC reset sequence and verified AP reset but not a transition S0 -> S5. TEST=Toggle EC GPIO PMIC_KPD_PWR_ODL and SYS_RST_L for a low pulse (see power_off function) to execute PMIC shutdown sequence and verified a power-lost transition S0 -> S5. Change-Id: I8ed789d701e834195865bfdf2d302388d42618d2 Signed-off-by: Tom Wai-Hong Tam <waihong@google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1028831 Commit-Ready: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>