Vincent Palatin ba98b92bbb cortex-m0: add more constraints on atomic implementation ...

In ARMv6-m instruction set, the load/store address register can only be
a "low" register : r0..r7.
Update the inline assembly constraints to match the hardware.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make buildall

Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd
Reviewed-on: https://chromium-review.googlesource.com/224582
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

2014-10-21 22:44:53 +00:00

..

cortex-m

stm32f: Add DMA interrupt handlers for channel 1 to 3

2014-10-21 00:44:39 +00:00

cortex-m0

cortex-m0: add more constraints on atomic implementation

2014-10-21 22:44:53 +00:00

host

Slow down time when running unit tests

2014-10-04 21:08:38 +00:00

nds32

Add cprints() and ccprints()

2014-05-21 20:32:17 +00:00