Vincent Palatin ba98b92bbb cortex-m0: add more constraints on atomic implementation ...

In ARMv6-m instruction set, the load/store address register can only be
a "low" register : r0..r7.
Update the inline assembly constraints to match the hardware.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=make buildall

Change-Id: I9872aeb437b2bb6401bed8076348e26d434320dd
Reviewed-on: https://chromium-review.googlesource.com/224582
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

2014-10-21 22:44:53 +00:00

..

atomic.h

cortex-m0: add more constraints on atomic implementation

2014-10-21 22:44:53 +00:00

build.mk

cortex-m0: add 64-bit multiplication

2014-07-10 21:17:58 +00:00

config_core.h

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00

cpu.c

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00

cpu.h

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00

div.S

better unhandled exception panic without runtime

2014-07-03 02:56:52 +00:00

ec.lds.S

zinger: check RW firmware signature

2014-10-02 23:18:25 +00:00

init.S

cortex-m0: stm32f0: use RW vector table when running RW code

2014-07-29 04:36:44 +00:00

irq_handler.h

stm32f: Add DMA interrupt handlers for channel 1 to 3

2014-10-21 00:44:39 +00:00

lmul.S

cortex-m0: add 64-bit multiplication

2014-07-10 21:17:58 +00:00

panic.c

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00

switch.S

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00

task.c

cortex-m0: disallow rescheduling if task_start() has not yet run

2014-10-07 01:29:33 +00:00

thumb_case.S

cortex-m0: add more thumb1 helpers

2014-04-11 20:02:07 +00:00

watchdog.c

Add Cortex-M0 core support

2014-03-11 05:52:41 +00:00