Kyoung Kim 80b997dc27 mec1322: fix gpio_disable_interrupt ...

MEC1322_INT_DISABLE(interrupt enable clear register) is 'Write 1 to Clear'
for each bit. To disable interrupt for specific GPIO pin, only specific
bit should be written with 1.

BUG=NONE
BRANCH=NONE
TEST=NONE

Change-Id: Ibf40a20656c4c99f9625b516cff3e7da9bf2f69d
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/309979
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>

2015-11-03 09:08:07 -08:00

..

g

cr50: upgrade to the latest FPGA image 20151029_41713@78167

2015-10-30 14:33:28 -07:00

host

cleanup: Put chip-specific configs in config_chip.h

2015-09-21 10:04:35 -07:00

it83xx

it8380dev: fix irq, jtag and system

2015-11-01 19:45:57 -08:00

lm4

cleanup: Put chip-specific configs in config_chip.h

2015-09-21 10:04:35 -07:00

mec1322

mec1322: fix gpio_disable_interrupt

2015-11-03 09:08:07 -08:00

npcx

nuc: Add state machines to handle i2c master stall bus and call i2c_xfer again.

2015-11-01 10:08:50 -08:00

nrf51

cleanup: Put chip-specific configs in config_chip.h

2015-09-21 10:04:35 -07:00

stm32

stm32f0: i2c: Set timing register values by port clock source

2015-10-30 14:33:29 -07:00