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mec1322: fix gpio_disable_interrupt

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MEC1322_INT_DISABLE(interrupt enable clear register) is 'Write 1 to Clear'
for each bit. To disable interrupt for specific GPIO pin, only specific
bit should be written with 1.

BUG=NONE
BRANCH=NONE
TEST=NONE

Change-Id: Ibf40a20656c4c99f9625b516cff3e7da9bf2f69d
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/309979
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Kyoung Kim
2015-11-02 09:56:01 -08:00
committed by chrome-bot
parent 59fd91317c
commit 80b997dc27
1 changed files with 1 additions and 1 deletions
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2
chip/mec1322/gpio.c
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@@ -168,7 +168,7 @@ int gpio_disable_interrupt(enum gpio_signal signal)
girq_id = int_map[port].girq_id;
bit_id = (port - int_map[port].port_offset) * 8 + i;
MEC1322_INT_DISABLE(girq_id) |= (1 << bit_id);
MEC1322_INT_DISABLE(girq_id) = (1 << bit_id);
return EC_SUCCESS;
}