Jett Rink bdcbd67fc2 lpc: Removing unnecessary register writes ...

According to Nuvoton datasheet, when SHM windows are in IO mode, only the
bottom 16-bits of registers @ offset xF4 and xF8 are used.

"This register is ignored when WRAM1_IO bit in WIN_CFG register is set to
1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This
register is set to its default value by Host Domain reset."

BRANCH=none
BUG=none
TEST=boot grunt and verify host communication still works.

Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/919006
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>

2018-02-16 15:12:18 -08:00

..

g

g: protect flash operations

2018-01-31 13:47:15 -08:00

host

test: store persistence files in RAM

2018-01-31 05:58:03 -08:00

ish

ish i2c: use i2c_ports[] to set bus speed

2017-12-13 00:32:23 -08:00

it83xx

it83xx: espi: workaround for changing PLL

2017-12-12 22:00:36 -08:00

lm4

host_events: Bump up host events and masks to 64-bit

2017-11-21 18:53:35 -08:00

mchp

chip/mchp: Default SPI image script verobse output to disabled

2018-02-09 19:03:26 -08:00

mec1322

system: Allow hibernate to clear AP_OFF flag

2017-12-05 18:00:38 -08:00

npcx

lpc: Removing unnecessary register writes

2018-02-16 15:12:18 -08:00

nrf51

cleanup: Remove jtag_pre_init()

2017-09-07 15:01:05 -07:00

stm32

stm32: add internal flash support for STM32H7 family

2018-02-09 05:24:47 -08:00