Files
OpenCellular/include
Vincent Palatin f23f45e74e cortex-m: enable I-cache on ARMv7-M
The ARMv7-M ISA defines standard (and optional) mechanism to manage the
CPU caches through the SCB (System Control Block) registers.
So far, only the Cortex-M7 core implements such as a mechanism (e.g. the
Cortex-M4 with caches we have are using a proprietary mechanism for the
management).

Define the functions to use the I-Cache,
and enable them on STM32H7 which is our only supported Cortex-M7 core.

The D-Cache mechanism is still To Be Done, as it involves a bit more
support in the firmware for the DMA memory areas.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR
(e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload
without crash and with a speed-up.

Change-Id: I6af1021d65048b787630387f7d95797db15d069c
Reviewed-on: https://chromium-review.googlesource.com/943445
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
2018-03-02 06:49:06 -08:00
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