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NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set so that the hardwire signals for SCI, SMI and RCIN are connected to VW input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has made it configurable. NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change ensures that they are preserved while initializing VWEVSM2 registers BUG=b:74111394 BRANCH=None TEST=Verified that SCI works on glkrvp and meowth with NPCX7. Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/943801 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
For an overview of the Embedded Controller firmware, refer to http://www.chromium.org/chromium-os/2014-firmware-summit For instructions on building from source, refer to http://www.chromium.org/chromium-os/ec-development/getting-started-building-ec-images-quickly