Hung-ying Tyan f3525ca990 pit: i2c: try unwedging the bus when i2c_xfer fails at sending START
and when the bus seems wedged at i2c_init().

BUG=chrome-os-partner:19286
TEST=Manual test on peach pit. Tried the following wedged cases:
(1) Bit bang a transaction but only read part of the response.
(Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 2 2
(2) Bit bang a transaction to do a "write" and stop while the other side is
acking.  (Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 1
(3) Same as (1) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
(Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 6 2
(4) Same as (2) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
(Refer to https://chromium-review.googlesource.com/#/c/66389)
Command to wedge: i2cwedge 0x90 0 5
(5) Manually pull down on SCL.
(Refer to https://chromium-review.googlesource.com/#/c/66063)

All five cases successfully wedged the bus and were recovered by this change.

BRANCH=pit

[dianders: made sure we don't change SCL after SCL high, misc other bits]

Change-Id: I23f16fcaa2a76ea37025f8204ab1cdb27e9ef6d1
Signed-off-by: Hung-ying Tyan <tyanh@chromium.org>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/66915
2013-08-29 22:55:10 +00:00
2013-08-23 17:16:19 -07:00
2013-04-29 23:31:28 -07:00
2012-05-11 09:11:52 -07:00
2011-12-08 19:18:06 +00:00

In the most general case, the flash layout looks something like this:

  +---------------------+
  | Reserved for EC use |
  +---------------------+

  +---------------------+
  |     Vblock B        |
  +---------------------+
  |  RW firmware B      |
  +---------------------+

  +---------------------+
  |     Vblock A        |
  +---------------------+
  |  RW firmware A      |
  +---------------------+

  +---------------------+
  |       FMAP          |
  +---------------------+
  |   Public root key   |
  +---------------------+
  |  Read-only firmware |
  +---------------------+


BIOS firmware (and kernel) put the vblock info at the start of each image
where it's easy to find. The Blizzard EC expects the firmware vector table
to come first, so we have to put the vblock at the end. This means we have
to know where to look for it, but that's built into the FMAP and the RO
firmware anyway, so that's not an issue.

The RO firmware doesn't need a vblock of course, but it does need some
reserved space for vboot-related things.

Using SHA256/RSA4096, the vblock is 2468 bytes (0x9a4), while the public
root key is 1064 bytes (0x428) and the current FMAP is 644 bytes (0x284). If
we reserve 4K at the top of each FW image, that should give us plenty of
room for vboot-related stuff.
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